- 09 Apr, 2021 40 commits
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Qu Huang authored
Here is the system crash log: [ 1272.884438] BUG: unable to handle kernel NULL pointer dereference at (null) [ 1272.884444] IP: [< (null)>] (null) [ 1272.884447] PGD 825b09067 PUD 8267c8067 PMD 0 [ 1272.884452] Oops: 0010 [#1] SMP [ 1272.884509] CPU: 13 PID: 3485 Comm: cat Kdump: loaded Tainted: G [ 1272.884515] task: ffff9a38dbd4d140 ti: ffff9a37cd3b8000 task.ti: ffff9a37cd3b8000 [ 1272.884517] RIP: 0010:[<0000000000000000>] [< (null)>] (null) [ 1272.884520] RSP: 0018:ffff9a37cd3bbe68 EFLAGS: 00010203 [ 1272.884522] RAX: 0000000000000000 RBX: 0000000000000000 RCX: 0000000000014d5f [ 1272.884524] RDX: fffffffffffffff4 RSI: 0000000000000001 RDI: ffff9a38aca4d200 [ 1272.884526] RBP: ffff9a37cd3bbed0 R08: ffff9a38dcd5f1a0 R09: ffff9a31ffc07300 [ 1272.884527] R10: ffff9a31ffc07300 R11: ffffffffaddd5e9d R12: ffff9a38b4e0fb00 [ 1272.884529] R13: 0000000000000001 R14: ffff9a37cd3bbf18 R15: ffff9a38aca4d200 [ 1272.884532] FS: 00007feccaa67740(0000) GS:ffff9a38dcd40000(0000) knlGS:0000000000000000 [ 1272.884534] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 1272.884536] CR2: 0000000000000000 CR3: 00000008267c0000 CR4: 00000000003407e0 [ 1272.884537] Call Trace: [ 1272.884544] [<ffffffffade68940>] ? seq_read+0x130/0x440 [ 1272.884548] [<ffffffffade40f8f>] vfs_read+0x9f/0x170 [ 1272.884552] [<ffffffffade41e4f>] SyS_read+0x7f/0xf0 [ 1272.884557] [<ffffffffae374ddb>] system_call_fastpath+0x22/0x27 [ 1272.884558] Code: Bad RIP value. [ 1272.884562] RIP [< (null)>] (null) [ 1272.884564] RSP <ffff9a37cd3bbe68> [ 1272.884566] CR2: 0000000000000000 Signed-off-by:
Qu Huang <jinsdb@126.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Bhaskar Chowdhury authored
s/seralization/serialization/ s/parallism/parallelism/ Acked-by:
Randy Dunlap <rdunlap@infradead.org> Signed-off-by:
Bhaskar Chowdhury <unixbhaskar@gmail.com> Signed-off-by:
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Tong Zhang authored
TTM_PL_VRAM may not initialized at all when calling radeon_bo_evict_vram(). We need to check before doing eviction. [ 2.160837] BUG: kernel NULL pointer dereference, address: 0000000000000020 [ 2.161212] #PF: supervisor read access in kernel mode [ 2.161490] #PF: error_code(0x0000) - not-present page [ 2.161767] PGD 0 P4D 0 [ 2.163088] RIP: 0010:ttm_resource_manager_evict_all+0x70/0x1c0 [ttm] [ 2.168506] Call Trace: [ 2.168641] radeon_bo_evict_vram+0x1c/0x20 [radeon] [ 2.168936] radeon_device_fini+0x28/0xf9 [radeon] [ 2.169224] radeon_driver_unload_kms+0x44/0xa0 [radeon] [ 2.169534] radeon_driver_load_kms+0x174/0x210 [radeon] [ 2.169843] drm_dev_register+0xd9/0x1c0 [drm] [ 2.170104] radeon_pci_probe+0x117/0x1a0 [radeon] Reviewed-by:
Christian König <christian.koenig@amd.com> Suggested-by:
Tong Zhang <ztong0001@gmail.com> Signed-off-by:
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Alex Sierra authored
Remove per_device_list from kfd_process and replace it with a kfd_process_device pointers array of MAX_GPU_INSTANCES size. This helps to manage the kfd_process_devices binded to a specific kfd_process. Also, functions used by kfd_chardev to iterate over the list were removed, since they are not valid anymore. Instead, it was replaced by a local loop iterating the array. Signed-off-by:
Alex Sierra <alex.sierra@amd.com> Signed-off-by:
Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by:
Jonathan Kim <jonathan.kim@amd.com> Signed-off-by:
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Aric Cyr authored
This version brings along following fixes: - Populate socclk entries for dcn2.1 - hide VGH asic specific structs - Add kernel doc to crc_rd_wrk field - revert max lb lines change - Log DMCUB trace buffer events - Fix debugfs link_settings entry - revert max lb use by default for n10 - Deallocate IRQ handlers on amdgpu_dm_irq_fini - Fixed Clock Recovery Sequence - Fix UBSAN: shift-out-of-bounds warning - [FW Promotion] Release 0.0.57 - Change input parameter for set_drr - Use pwrseq instance to determine eDP instance Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Acked-by:
Solomon Chiu <solomon.chiu@amd.com> Signed-off-by:
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Jake Wang authored
[Why & How] Link index doesn't always correspond to the appropriate eDP instance. We can assume lower link index is a lower eDP instance and set panel control instance accordingly. Tested-by:
Jake Wang <haonan.wang2@amd.com> Reviewed-by:
Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by:
Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by:
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Alvin Lee authored
[Why] Change set_drr to pass in the entire dc_crtc_timing_adjust structure instead of passing in the parameters individually. This is to more easily pass in required parameters in the adjust structure when it gets updated. Tested-by:
Alvin Lee <alvin.lee2@amd.com> Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
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Anthony Koo authored
Tested-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
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Anson Jacob authored
[Why] On NAVI14 CONFIG_UBSAN reported shift-out-of-bounds at display_rq_dlg_calc_20v2.c:304:38 rq_param->misc.rq_c.blk256_height is 0 when chroma(*_c) is invalid. dml_log2 returns -1023 for log2(0), although log2(0) is undefined. Which ended up as: rq_param->dlg.rq_c.swath_height = 1 << -1023 [How] Fix applied on all dml versions. 1. Ensure dml_log2 is only called if the argument is greater than 0. 2. Subtract req128_l/req128_c from log2_swath_height_l/log2_swath_height_c only when it is greater than 0. Tested-by:
Anson Jacob <Anson.Jacob@amd.com> Reviewed-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by:
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David Galiffi authored
[Why] When performing clock recovery, if a pre-emphasis adjustment is requested, but voltage swing remains constant, the the retry counter will not be reset. This can lead to prematurely failing link training. [How] Reset the clock recovery retry counter if an adjustment is requested for either voltage swing or pre-emphasis. Tested-by:
Calvin Hou <Calvin.Hou@amd.com> Signed-off-by:
David Galiffi <David.Galiffi@amd.com> Reviewed-by:
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Victor Lu authored
[why] The amdgpu_dm IRQ handlers are not freed during the IRQ teardown. [how] Add function to deallocate IRQ handlers on amdgpu_dm_irq_fini step. Tested-by:
Victor Lu <victorchengchi.lu@amd.com> Reviewed-by:
Roman Li <Roman.Li@amd.com> Acked-by:
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Dmytro Laktyushkin authored
This is causing a pstate change underflow regression for unknown reason Tested-by:
Eric Bernstein <Eric.Bernstein@amd.com> Acked-by:
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Fangzhi Zuo authored
1. Catch invalid link_rate and link_count settings 2. Call dc interface to overwrite preferred link settings, and wait until next stream update to apply the new settings. Tested-by:
Fangzhi Zuo <Jerry.Zuo@amd.com> Reviewed-by:
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Leo (Hanghong) Ma authored
[Why] We want to log DMCUB trace buffer events as Linux kernel traces. [How] Register an IRQ handler for DMCUB outbox0 interrupt in amdgpu_dm, and log the messages in the DMCUB tracebuffer to a new DMCUB TRACE_EVENT as soon as we receive the outbox0 IRQ from DMCUB FW. Tested-by:
Leo (Hanghong) Ma <hanghong.ma@amd.com> Reviewed-by:
Harry Wentland <Harry.Wentland@amd.com> Acked-by:
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Dmytro Laktyushkin authored
Some hardware revisions do have a max number of lines limitation not honouring which can cause pstate switch underflow. Tested-by:
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Wayne Lin authored
[Why] Receive warning message below: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h:380: warning: Function parameter or member 'crc_rd_wrk' not described in 'amdgpu_display_manager' [How] Add documentation for crc_rd_wrk. Tested-by:
Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by:
Wayne Lin <Wayne.Lin@amd.com> Reviewed-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by:
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Dmytro Laktyushkin authored
The pmfw structs are specific to the asic and should not be present in base clk_mgr struct v2: squash in SI fix (Alex) Tested-by:
Eric Yang <eric.yang2@amd.com> Acked-by:
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Roman Li authored
[Why] Dcn2.1 socclk entries in bandwidth params are not initialized. They are not used now, but will be needed for dml validation. [How] Populate socclk bw params from dpm clock table Tested-by:
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xinhui pan authored
To make size is 4 byte aligned. Use &~0x3ULL instead of &3ULL. Signed-off-by:
xinhui pan <xinhui.pan@amd.com> Reviewed-by:
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Guchun Chen authored
Instead of blocking varied unsupported MP1 state in upper level, defer and skip such MP1 state handling in specific ASIC. Signed-off-by:
Lijo Lazar <lijo.lazar@amd.com> Signed-off-by:
Guchun Chen <guchun.chen@amd.com> Reviewed-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
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Guchun Chen authored
Skip PP_MP1_STATE_NONE in MP1 state setting, otherwise, it will break S3 sequence. [ 50.188269] [drm:amdgpu_device_ip_suspend_phase2 [amdgpu]] *ERROR* SMC failed to set mp1 state 0, -22 [ 50.969901] amdgpu 0000:03:00.0: amdgpu: SMU is resuming... [ 50.970024] sd 0:0:0:0: [sda] Starting disk [ 50.979723] serial 00:02: activated [ 51.353644] ata4: SATA link down (SStatus 4 SControl 300) [ 51.353669] ata3: SATA link down (SStatus 4 SControl 300) [ 51.353747] ata6: SATA link down (SStatus 4 SControl 300) [ 51.357694] ata1: SATA link up 6.0 Gbps (SStatus 133 SControl 300) [ 51.357711] ata5: SATA link down (SStatus 4 SControl 300) [ 51.357729] ata2: SATA link down (SStatus 4 SControl 300) [ 51.358005] ata1.00: supports DRM functions and may not be fully accessible [ 51.360491] ata1.00: supports DRM functions and may not be fully accessible [ 51.362573] ata1.00: configured for UDMA/133 [ 51.362610] ahci 0000:00:17.0: port does not support device sleep [ 51.362946] ata1.00: Enabling discard_zeroes_data [ 52.566438] amdgpu 0000:03:00.0: amdgpu: Msg issuing pre-check failed and SMU may be not in the right state! [ 54.126316] amdgpu 0000:03:00.0: amdgpu: Msg issuing pre-check failed and SMU may be not in the right state! [ 54.126317] amdgpu 0000:03:00.0: amdgpu: Failed to SetDriverDramAddr! [ 54.126318] amdgpu 0000:03:00.0: amdgpu: Failed to setup smc hw! [ 54.126319] [drm:amdgpu_device_ip_resume_phase2 [amdgpu]] *ERROR* resume of IP block <smu> failed -62 [ 54.126398] amdgpu 0000:03:00.0: amdgpu: amdgpu_device_ip_resume failed (-62). [ 54.126399] PM: dpm_run_callback(): pci_pm_resume+0x0/0x90 returns -62 [ 54.126403] PM: Device 0000:03:00.0 failed to resume async: error -62 Fixes: 1689fca0 ("drm/amd/pm: fix Navi1x runtime resume failure V2") Signed-off-by:
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Shirish S authored
refactor AMDGPU_PP_SENSOR_GPU_LOAD to ensure code consistency with other commands Signed-off-by:
Shirish S <shirish.s@amd.com> Reviewed-by:
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Nirmoy Das authored
Fix size comparison in the resource cursor. Signed-off-by:
Nirmoy Das <nirmoy.das@amd.com> Reviewed-by:
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Alex Deucher authored
Commit 09821499 added fetching of the AUX_DPHY register values from the vbios, but it also changed the default values in the case when there are no values in the vbios. This causes problems with displays with high refresh rates. To fix this, switch back to the original default value for AUX_DPHY_TX_CONTROL. Fixes: 09821499 ("drm/amd/display: Read VBIOS Golden Settings Tbl") Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1426Reviewed-by:
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Nirmoy Das authored
Replace GFP_KERNEL with GFP_ATOMIC as dcn20_resource_construct() can't sleep. Partially fixes: https://bugzilla.kernel.org/show_bug.cgi?id=212311 as dcn20_resource_construct() also calls into SMU functions which does mutex_lock(). Reviewed-by:
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Lee Jones authored
Fixes the following W=1 kernel build warning(s): drivers/gpu/drm/amd/amdgpu/../display/dc/calcs/dce_calcs.c: In function ‘bw_calcs_init’: drivers/gpu/drm/amd/amdgpu/../display/dc/calcs/dce_calcs.c:2726:1: warning: the frame size of 1336 bytes is larger than 1024 bytes [-Wframe-larger-than=] v2: squash in sizeof fix Cc: Harry Wentland <harry.wentland@amd.com> Cc: Leo Li <sunpeng.li@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: "Christian König" <christian.koenig@amd.com> Cc: David Airlie <airlied@linux.ie> Cc: Daniel Vetter <daniel@ffwll.ch> Cc: amd-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org Reviewed-by:
Lee Jones <lee.jones@linaro.org> Signed-off-by:
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Lee Jones authored
Fixes the following W=1 kernel build warning(s): drivers/gpu/drm/amd/amdgpu/../display/dc/calcs/dce_calcs.c: In function ‘calculate_bandwidth’: drivers/gpu/drm/amd/amdgpu/../display/dc/calcs/dce_calcs.c:2016:1: warning: the frame size of 1216 bytes is larger than 1024 bytes [-Wframe-larger-than=] Cc: Harry Wentland <harry.wentland@amd.com> Cc: Leo Li <sunpeng.li@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: "Christian König" <christian.koenig@amd.com> Cc: David Airlie <airlied@linux.ie> Cc: Daniel Vetter <daniel@ffwll.ch> Cc: Colin Ian King <colin.king@canonical.com> Cc: amd-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org Reviewed-by:
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Lee Jones authored
Fixes the following W=1 kernel build warning(s): drivers/gpu/drm/amd/amdgpu/../display/dc/dce80/dce80_resource.c:527:17: warning: no previous prototype for ‘dce80_aux_engine_create’ [-Wmissing-prototypes] drivers/gpu/drm/amd/amdgpu/../display/dc/dce80/dce80_resource.c:565:20: warning: no previous prototype for ‘dce80_i2c_hw_create’ [-Wmissing-prototypes] drivers/gpu/drm/amd/amdgpu/../display/dc/dce80/dce80_resource.c:581:20: warning: no previous prototype for ‘dce80_i2c_sw_create’ [-Wmissing-prototypes] drivers/gpu/drm/amd/amdgpu/../display/dc/dce80/dce80_resource.c:715:22: warning: no previous prototype for ‘dce80_link_encoder_create’ [-Wmissing-prototypes] drivers/gpu/drm/amd/amdgpu/../display/dc/dce80/dce80_resource.c:754:22: warning: no previous prototype for ‘dce80_clock_source_create’ [-Wmissing-prototypes] drivers/gpu/drm/amd/amdgpu/../display/dc/dce80/dce80_resource.c:778:6: warning: no previous prototype for ‘dce80_clock_source_destroy’ [-Wmissing-prototypes] drivers/gpu/drm/amd/amdgpu/../display/dc/dce80/dce80_resource.c:868:6: warning: no previous prototype for ‘dce80_validate_bandwidth’ [-Wmissing-prototypes] drivers/gpu/drm/amd/amdgpu/../display/dc/dce80/dce80_resource.c:913:16: warning: no previous prototype for ‘dce80_validate_global’ [-Wmissing-prototypes] Cc: Harry Wentland <harry.wentland@amd.com> Cc: Leo Li <sunpeng.li@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: "Christian König" <christian.koenig@amd.com> Cc: David Airlie <airlied@linux.ie> Cc: Daniel Vetter <daniel@ffwll.ch> Cc: Anthony Koo <Anthony.Koo@amd.com> Cc: amd-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org Reviewed-by:
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Evan Quan authored
The RLC was put into a wrong state on runtime suspend. Thus the RLC autoload will fail on the succeeding runtime resume. By adding an intermediate PPSMC_MSG_PrepareMp1ForUnload(some GC hard reset involved, designed for PnP), we can bring RLC back into the desired state. V2: integrate INTERRUPTS_ENABLED flag clearing into current mp1 state set routines Signed-off-by: -
Lijo Lazar authored
Enable clockgating for VCN and JPEG blocks on aldebaran Signed-off-by:
Hawking Zhang <Hawking.Zhang@amd.com> Acked-by:
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Bhaskar Chowdhury authored
s/proces/process/ Signed-off-by:
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Bhaskar Chowdhury authored
s/traing/training/ ...Plus the entire sentence construction for better readability. Signed-off-by:
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Daniel Gomez authored
If userptr pages have been pinned but not bounded, they remain uncleared. Reviewed-by:
Daniel Gomez <daniel@qtec.com> Signed-off-by:
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Daniel Gomez authored
If userptr pages have been pinned but not bounded, they remain uncleared. Reviewed-by:
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Alex Deucher authored
GFX is in gfxoff mode during s0ix so we shouldn't need to actually tear anything down and restore it. Acked-by:
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Alex Deucher authored
We handle it properly within the CG/PG functions directly now. Acked-by:
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Pratik Vishwakarma authored
Not needed as the device is in gfxoff state so the CG/PG state is handled just like it would be for gfxoff during runtime gfxoff. This should also prevent delays on resume. Reworked from Pratik's original patch (Alex) Acked-by:
Pratik Vishwakarma <Pratik.Vishwakarma@amd.com>
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Alex Deucher authored
Provide and explanation as to why we skip GFX and PSP for S0ix. GFX goes into gfxoff, same as runtime, so no need to tear down and re-init. PSP is part of the always on state, so no need to touch it. Acked-by:
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Alex Deucher authored
The SMU expects CGPG to be enabled when entering S0ix. with this we can re-enable SMU suspend. Acked-by:
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Alex Deucher authored
This really needs to be done to properly tear down the device. SMC, PSP, and GFX are still problematic, need to dig deeper into what aspect of them that is problematic. Acked-by:
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