- 09 Jun, 2023 40 commits
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James Zhu authored
VCN4.0.3 used up to 16 doorbells per partition. Signed-off-by:
James Zhu <James.Zhu@amd.com> Reviewed-by:
Leo Liu <leo.liu@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Amber Lin authored
Set F8_MODE for GC 9.4.3 as optimal/non-IEEE. Also update gc_v9_0 to gc_v9_4_3 to include more definitions such as the F8_MODE bit, and remove unused header files. v2: fix IP version check (Alex) Signed-off-by:
Amber Lin <Amber.Lin@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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James Zhu authored
Add multiple jpeg rings support for vcn4_0_3 Signed-off-by:
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James Zhu authored
Add multiple jpeg rings support. Signed-off-by:
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James Zhu authored
Enable vcn DPG mode for VCN4_0_3. Signed-off-by:
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James Zhu authored
Enable vcn pg for VCN4_0_3. Signed-off-by:
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James Zhu authored
Enable vcn cg for VCN4_0_3. Signed-off-by:
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James Zhu authored
Enable jpeg pg for VCN4_0_3. Signed-off-by:
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James Zhu authored
Enable jpeg cg for VCN4_0_3. Signed-off-by:
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James Zhu authored
Add vcn support for VCN4_0_3. Signed-off-by:
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James Zhu authored
Add jpeg support for VCN4_0_3. v2: squash in delayed work typo fix (Alex) Signed-off-by:
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James Zhu authored
Add VCN4_0_3 firmware. v2: fix fw name (Alex) Signed-off-by:
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Hawking Zhang authored
Add vcn v4_0_3 register offset adn shift masks header files v2: update headers (Alex) Signed-off-by:
Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by:
Le Ma <Le.Ma@amd.com> Signed-off-by:
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James Zhu authored
Add more macro to support offset variant and simplify macro SOC15_WAIT_ON_RREG. Signed-off-by:
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Lijo Lazar authored
Use SOC15 API so that the register offset is calculated correctly. Signed-off-by:
Lijo Lazar <lijo.lazar@amd.com> Reviewed-by:
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Amber Lin authored
New GC (v9.4.3) and ATHUB (v1.8.0) versions are used. Add kgd_gfx_v9_4_3_* functions if registers in use of kgd_gfx_v9_* functions are changed or have different offset. Signed-off-by:
Mukul Joshi <mukul.joshi@amd.com> Signed-off-by:
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Shiwu Zhang authored
There are AMDGPU_MAX_VMHUBS of vmhub in maximum and need to init the vm_inv_engs for all of them. In this way, the below error can be ruled out. [ 217.317752] amdgpu 0000:02:00.0: amdgpu: no VM inv eng for ring sdma0 Signed-off-by:
Shiwu Zhang <shiwu.zhang@amd.com> Reviewed-by:
Christian Koenig <Christian.Koenig@amd.com> Reviewed-by:
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Shiwu Zhang authored
Add a module parameter to override the partition mode. Signed-off-by:
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Shiwu Zhang authored
To write regs on different GCDs, use the inst index. Signed-off-by:
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Le Ma authored
Add current/available compute partitin mode sysfs node. v2: make the sysfs node as IP independent one in amdgpu_gfx.c Signed-off-by:
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Le Ma authored
Pass the xcc_id to AMDGPU_GFXHUB(x) Signed-off-by:
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Le Ma authored
Each XCD owns one GFXHUB. v2: switch to the new VMHUB layout Signed-off-by:
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Le Ma authored
As the layout of VMHUB definition has been changed to cover multiple XCD/AID case, the original num_vmhubs is not appropriate to do vmhub iteration any more. Drop num_vmhubs and introduce vmhubs_mask instead. v2: switch to the new VMHUB layout v3: use DECLARE_BITMAP to define vmhubs_mask Signed-off-by:
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Le Ma authored
Each XCD has its own gfxhub. v2: switch to the new VMHUB layout v3: fix mistake Signed-off-by:
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Hawking Zhang authored
v1: Each partition has its own gfxhub or mmhub. adjust the num of MAX_VMHUBS and the GFXHUB/MMHUB layout (Le) v2: re-design the AMDGPU_GFXHUB/AMDGPU_MMHUB layout (Le) v3: apply the gfxhub/mmhub layout to new IPs (Hawking) v4: fix up gmc11 (Alex) v5: rebase (Alex) Signed-off-by:
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Aric Cyr authored
Acked-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
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Daniel Miess authored
[Why] Calls to dcn20_adjust_freesync_v_startup are no longer needed as of dcn3+ and can cause underflow in some cases [How] Move calls to dcn20_adjust_freesync_v_startup up into validate_bandwidth for dcn2.x Reviewed-by:
Jun Lei <jun.lei@amd.com> Acked-by:
Daniel Miess <daniel.miess@amd.com> Tested-by:
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Rodrigo Siqueira authored
There is no need to use dc_version in the dc_construct_ctx since this value is copied to dc_ctx->dce_version later. This commit removes the extra steps. Reviewed-by:
Alex Hung <alex.hung@amd.com> Acked-by:
Rodrigo Siqueira <rodrigo.siqueira@amd.com> Tested-by:
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Alvin Lee authored
[Description] - Updates to unbounded requesting should not be conditional on updates to dlg / ttu, as this could prevent unbounded requesting from being updated if dlg / ttu does not change Reviewed-by:
Alvin Lee <alvin.lee2@amd.com> Tested-by:
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Leo (Hanghong) Ma authored
[Why && How] We would like to have visual confirm color support for MCLK switch. 1. Set visual confirm color to yellow: Vblank MCLK switch. 2. Set visual confirm color to cyan: FPO + Vblank MCLK switch. 3. Set visual confirm color to pink: Vactive MCLK switch. Reviewed-by:
Leo (Hanghong) Ma <hanghong.ma@amd.com> Tested-by:
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Daniel Miess authored
[Why] Underflow observed when using a display with a large vblank region and low refresh rate [How] Simplify calculation of vblank_nom Increase value for VBlankNomDefaultUS to 800us Reviewed-by:
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Rodrigo Siqueira authored
To improve the readability of the of the log, this commit introduces a function that converts the signal type id to a human-readable string. Reviewed-by:
Jerry Zuo <jerry.zuo@amd.com> Acked-by:
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Alvin Lee authored
[Description] - Some 1920x1080@60hz displays have VBLANK time > 600us which we still want to accept for FPO + Vactive configs based on testing - Increase max VBLANK time to 1000us to allow these configs for FPO + Vactive - Increase minimum vactive switch margin for FPO + Vactive to 200us - Based on testing, 1920x1080@120hz can have a switch margin of ~160us which requires significantly longer FPO stretch margin (5ms) which we don't want to accept for now - Also move margins into debug option Reviewed-by:
Nevenko Stupar <nevenko.stupar@amd.com> Acked-by:
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Alvin Lee authored
[Description] - Update clocks is skipped in the GPU overclock sequence - However, we still need to update DISPCLK, DPPCLK, and DTBCLK because the GPU overclock sequence could temporarily disable ODM 2:1 combine because we disable all planes in the sequence Reviewed-by:
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Mustapha Ghaddar authored
Use dpia_validate_usb4_bw() function Fixes: a8b53760 ("drm/amd/display: Add function pointer for validate bw usb4") Reviewed-by:
Roman Li <roman.li@amd.com> Reviewed-by:
Meenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com> Acked-by:
Mustapha Ghaddar <mghaddar@amd.com> Tested-by:
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Evan Quan authored
PMFW may boots the ASIC with a different power mode from the system's real one. Notify PMFW explicitly the power mode the system in. This is needed only when ACDC switch via gpio is not supported. Signed-off-by:
Evan Quan <evan.quan@amd.com> Reviewed-by:
Kenneth Feng <kenneth.feng@amd.com> Signed-off-by:
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Guchun Chen authored
When performing device unbind or halt, we have disabled all irqs at the very begining like amdgpu_pci_remove or amdgpu_device_halt. So amdgpu_irq_put for irqs stored in fence driver should not be called any more, otherwise, below calltrace will arrive. [ 139.114088] WARNING: CPU: 2 PID: 1550 at drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c:616 amdgpu_irq_put+0xf6/0x110 [amdgpu] [ 139.114655] Call Trace: [ 139.114655] <TASK> [ 139.114657] amdgpu_fence_driver_hw_fini+0x93/0x130 [amdgpu] [ 139.114836] amdgpu_device_fini_hw+0xb6/0x350 [amdgpu] [ 139.114955] amdgpu_driver_unload_kms+0x51/0x70 [amdgpu] [ 139.115075] amdgpu_pci_remove+0x63/0x160 [amdgpu] [ 139.115193] ? __pm_runtime_resume+0x64/0x90 [ 139.115195] pci_device_remove+0x3a/0xb0 [ 139.115197] device_remove+0x43/0x70 [ 139.115198] device_release_driver_internal+0xbd/0x140 Signed-off-by:
Guchun Chen <guchun.chen@amd.com> Acked-by:
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Alex Sierra authored
Accomplish this by reading the seq number right away instead of sleep for 5us. There are certain cases where the fence is ready almost immediately. Sleep number granularity was also reduced as the majority of the kiq tlb flush takes between 2us to 6us. Signed-off-by:
Alex Sierra <alex.sierra@amd.com> Acked-by:
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Alex Deucher authored
Implement get_vbios_fb_size() so we can properly reserve the vbios splash screen to avoid potential artifacts on the screen during the transition from the pre-OS console to the OS console. Acked-by:
Sunil Khatri <sunil.khatri@amd.com> Signed-off-by:
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Jiapeng Chong authored
./drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c:586:37-39: WARNING !A || A && B is equivalent to !A || B. ./drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c:595:37-39: WARNING !A || A && B is equivalent to !A || B. Reported-by:
Abaci Robot <abaci@linux.alibaba.com> Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=4941Signed-off-by:
Jiapeng Chong <jiapeng.chong@linux.alibaba.com> Signed-off-by:
Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by:
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