1. 30 Oct, 2023 10 commits
    • Oliver Upton's avatar
      Merge branch kvm-arm64/stage2-vhe-load into kvmarm/next · df26b779
      Oliver Upton authored
      * kvm-arm64/stage2-vhe-load:
        : Setup stage-2 MMU from vcpu_load() for VHE
        :
        : Unlike nVHE, there is no need to switch the stage-2 MMU around on guest
        : entry/exit in VHE mode as the host is running at EL2. Despite this KVM
        : reloads the stage-2 on every guest entry, which is needless.
        :
        : This series moves the setup of the stage-2 MMU context to vcpu_load()
        : when running in VHE mode. This is likely to be a win across the board,
        : but also allows us to remove an ISB on the guest entry path for systems
        : with one of the speculative AT errata.
        KVM: arm64: Move VTCR_EL2 into struct s2_mmu
        KVM: arm64: Load the stage-2 MMU context in kvm_vcpu_load_vhe()
        KVM: arm64: Rename helpers for VHE vCPU load/put
        KVM: arm64: Reload stage-2 for VMID change on VHE
        KVM: arm64: Restore the stage-2 context in VHE's __tlb_switch_to_host()
        KVM: arm64: Don't zero VTTBR in __tlb_switch_to_host()
      Signed-off-by: default avatarOliver Upton <oliver.upton@linux.dev>
      df26b779
    • Oliver Upton's avatar
      Merge branch kvm-arm64/nv-trap-fixes into kvmarm/next · 51e60796
      Oliver Upton authored
      * kvm-arm64/nv-trap-fixes:
        : NV trap forwarding fixes, courtesy Miguel Luis and Marc Zyngier
        :
        :  - Explicitly define the effects of HCR_EL2.NV on EL2 sysregs in the
        :    NV trap encoding
        :
        :  - Make EL2 registers that access AArch32 guest state UNDEF or RAZ/WI
        :    where appropriate for NV guests
        KVM: arm64: Handle AArch32 SPSR_{irq,abt,und,fiq} as RAZ/WI
        KVM: arm64: Do not let a L1 hypervisor access the *32_EL2 sysregs
        KVM: arm64: Refine _EL2 system register list that require trap reinjection
        arm64: Add missing _EL2 encodings
        arm64: Add missing _EL12 encodings
      Signed-off-by: default avatarOliver Upton <oliver.upton@linux.dev>
      51e60796
    • Oliver Upton's avatar
      Merge branch kvm-arm64/smccc-filter-cleanups into kvmarm/next · 25a35c1a
      Oliver Upton authored
      * kvm-arm64/smccc-filter-cleanups:
        : Cleanup the management of KVM's SMCCC maple tree
        :
        : Avoid the cost of maintaining the SMCCC filter maple tree if userspace
        : hasn't writen a rule to the filter. While at it, rip out the now
        : unnecessary VM flag to indicate whether or not the SMCCC filter was
        : configured.
        KVM: arm64: Use mtree_empty() to determine if SMCCC filter configured
        KVM: arm64: Only insert reserved ranges when SMCCC filter is used
        KVM: arm64: Add a predicate for testing if SMCCC filter is configured
      Signed-off-by: default avatarOliver Upton <oliver.upton@linux.dev>
      25a35c1a
    • Oliver Upton's avatar
      Merge branch kvm-arm64/pmevtyper-filter into kvmarm/next · 7ff7dfe9
      Oliver Upton authored
      * kvm-arm64/pmevtyper-filter:
        : Fixes to KVM's handling of the PMUv3 exception level filtering bits
        :
        :  - NSH (count at EL2) and M (count at EL3) should be stateful when the
        :    respective EL is advertised in the ID registers but have no effect on
        :    event counting.
        :
        :  - NSU and NSK modify the event filtering of EL0 and EL1, respectively.
        :    Though the kernel may not use these bits, other KVM guests might.
        :    Implement these bits exactly as written in the pseudocode if EL3 is
        :    advertised.
        KVM: arm64: Add PMU event filter bits required if EL3 is implemented
        KVM: arm64: Make PMEVTYPER<n>_EL0.NSH RES0 if EL2 isn't advertised
      Signed-off-by: default avatarOliver Upton <oliver.upton@linux.dev>
      7ff7dfe9
    • Oliver Upton's avatar
      Merge branch kvm-arm64/feature-flag-refactor into kvmarm/next · d47dcb67
      Oliver Upton authored
      * kvm-arm64/feature-flag-refactor:
        : vCPU feature flag cleanup
        :
        : Clean up KVM's handling of vCPU feature flags to get rid of the
        : vCPU-scoped bitmaps and remove failure paths from kvm_reset_vcpu().
        KVM: arm64: Get rid of vCPU-scoped feature bitmap
        KVM: arm64: Remove unused return value from kvm_reset_vcpu()
        KVM: arm64: Hoist NV+SVE check into KVM_ARM_VCPU_INIT ioctl handler
        KVM: arm64: Prevent NV feature flag on systems w/o nested virt
        KVM: arm64: Hoist PAuth checks into KVM_ARM_VCPU_INIT ioctl
        KVM: arm64: Hoist SVE check into KVM_ARM_VCPU_INIT ioctl handler
        KVM: arm64: Hoist PMUv3 check into KVM_ARM_VCPU_INIT ioctl handler
        KVM: arm64: Add generic check for system-supported vCPU features
      Signed-off-by: default avatarOliver Upton <oliver.upton@linux.dev>
      d47dcb67
    • Oliver Upton's avatar
      Merge branch kvm-arm64/misc into kvmarm/next · 054056bf
      Oliver Upton authored
      * kvm-arm64/misc:
        : Miscellaneous updates
        :
        :  - Put an upper bound on the number of I-cache invalidations by
        :    cacheline to avoid soft lockups
        :
        :  - Get rid of bogus refererence count transfer for THP mappings
        :
        :  - Do a local TLB invalidation on permission fault race
        :
        :  - Fixes for page_fault_test KVM selftest
        :
        :  - Add a tracepoint for detecting MMIO instructions unsupported by KVM
        KVM: arm64: Add tracepoint for MMIO accesses where ISV==0
        KVM: arm64: selftest: Perform ISB before reading PAR_EL1
        KVM: arm64: selftest: Add the missing .guest_prepare()
        KVM: arm64: Always invalidate TLB for stage-2 permission faults
        KVM: arm64: Do not transfer page refcount for THP adjustment
        KVM: arm64: Avoid soft lockups due to I-cache maintenance
        arm64: tlbflush: Rename MAX_TLBI_OPS
        KVM: arm64: Don't use kerneldoc comment for arm64_check_features()
      Signed-off-by: default avatarOliver Upton <oliver.upton@linux.dev>
      054056bf
    • Oliver Upton's avatar
      KVM: arm64: Add tracepoint for MMIO accesses where ISV==0 · d11974dc
      Oliver Upton authored
      It is a pretty well known fact that KVM does not support MMIO emulation
      without valid instruction syndrome information (ESR_EL2.ISV == 0). The
      current kvm_pr_unimpl() is pretty useless, as it contains zero context
      to relate the event to a vCPU.
      
      Replace it with a precise tracepoint that dumps the relevant context
      so the user can make sense of what the guest is doing.
      Acked-by: default avatarZenghui Yu <yuzenghui@huawei.com>
      Acked-by: default avatarMarc Zyngier <maz@kernel.org>
      Link: https://lore.kernel.org/r/20231026205306.3045075-1-oliver.upton@linux.devSigned-off-by: default avatarOliver Upton <oliver.upton@linux.dev>
      d11974dc
    • Zenghui Yu's avatar
      KVM: arm64: selftest: Perform ISB before reading PAR_EL1 · 06899aa5
      Zenghui Yu authored
      It looks like a mistake to issue ISB *after* reading PAR_EL1, we should
      instead perform it between the AT instruction and the reads of PAR_EL1.
      
      As according to DDI0487J.a IJTYVP,
      
      "When an address translation instruction is executed, explicit
       synchronization is required to guarantee the result is visible to
       subsequent direct reads of PAR_EL1."
      
      Otherwise all guest_at testcases fail on my box with
      
      ==== Test Assertion Failure ====
        aarch64/page_fault_test.c:142: par & 1 == 0
        pid=1355864 tid=1355864 errno=4 - Interrupted system call
           1	0x0000000000402853: vcpu_run_loop at page_fault_test.c:681
           2	0x0000000000402cdb: run_test at page_fault_test.c:730
           3	0x0000000000403897: for_each_guest_mode at guest_modes.c:100
           4	0x00000000004019f3: for_each_test_and_guest_mode at page_fault_test.c:1105
           5	 (inlined by) main at page_fault_test.c:1131
           6	0x0000ffffb153c03b: ?? ??:0
           7	0x0000ffffb153c113: ?? ??:0
           8	0x0000000000401aaf: _start at ??:?
        0x1 != 0x0 (par & 1 != 0)
      Signed-off-by: default avatarZenghui Yu <yuzenghui@huawei.com>
      Acked-by: default avatarMarc Zyngier <maz@kernel.org>
      Link: https://lore.kernel.org/r/20231007124043.626-2-yuzenghui@huawei.comSigned-off-by: default avatarOliver Upton <oliver.upton@linux.dev>
      06899aa5
    • Zenghui Yu's avatar
      KVM: arm64: selftest: Add the missing .guest_prepare() · beaf35b4
      Zenghui Yu authored
      Running page_fault_test on a Cortex A72 fails with
      
      Test: ro_memslot_no_syndrome_guest_cas
      Testing guest mode: PA-bits:40,  VA-bits:48,  4K pages
      Testing memory backing src type: anonymous
      ==== Test Assertion Failure ====
        aarch64/page_fault_test.c:117: guest_check_lse()
        pid=1944087 tid=1944087 errno=4 - Interrupted system call
           1	0x00000000004028b3: vcpu_run_loop at page_fault_test.c:682
           2	0x0000000000402d93: run_test at page_fault_test.c:731
           3	0x0000000000403957: for_each_guest_mode at guest_modes.c:100
           4	0x00000000004019f3: for_each_test_and_guest_mode at page_fault_test.c:1108
           5	 (inlined by) main at page_fault_test.c:1134
           6	0x0000ffff868e503b: ?? ??:0
           7	0x0000ffff868e5113: ?? ??:0
           8	0x0000000000401aaf: _start at ??:?
        guest_check_lse()
      
      because we don't have a guest_prepare stage to check the presence of
      FEAT_LSE and skip the related guest_cas testing, and we end-up failing in
      GUEST_ASSERT(guest_check_lse()).
      
      Add the missing .guest_prepare() where it's indeed required.
      Signed-off-by: default avatarZenghui Yu <yuzenghui@huawei.com>
      Acked-by: default avatarMarc Zyngier <maz@kernel.org>
      Link: https://lore.kernel.org/r/20231007124043.626-1-yuzenghui@huawei.comSigned-off-by: default avatarOliver Upton <oliver.upton@linux.dev>
      beaf35b4
    • Oliver Upton's avatar
      KVM: arm64: Always invalidate TLB for stage-2 permission faults · be097997
      Oliver Upton authored
      It is possible for multiple vCPUs to fault on the same IPA and attempt
      to resolve the fault. One of the page table walks will actually update
      the PTE and the rest will return -EAGAIN per our race detection scheme.
      KVM elides the TLB invalidation on the racing threads as the return
      value is nonzero.
      
      Before commit a12ab137 ("KVM: arm64: Use local TLBI on permission
      relaxation") KVM always used broadcast TLB invalidations when handling
      permission faults, which had the convenient property of making the
      stage-2 updates visible to all CPUs in the system. However now we do a
      local invalidation, and TLBI elision leads to the vCPU thread faulting
      again on the stale entry. Remember that the architecture permits the TLB
      to cache translations that precipitate a permission fault.
      
      Invalidate the TLB entry responsible for the permission fault if the
      stage-2 descriptor has been relaxed, regardless of which thread actually
      did the job.
      Acked-by: default avatarMarc Zyngier <maz@kernel.org>
      Link: https://lore.kernel.org/r/20230922223229.1608155-1-oliver.upton@linux.devSigned-off-by: default avatarOliver Upton <oliver.upton@linux.dev>
      be097997
  2. 25 Oct, 2023 5 commits
  3. 24 Oct, 2023 2 commits
  4. 23 Oct, 2023 1 commit
    • Marc Zyngier's avatar
      KVM: arm64: Move VTCR_EL2 into struct s2_mmu · fe49fd94
      Marc Zyngier authored
      We currently have a global VTCR_EL2 value for each guest, even
      if the guest uses NV. This implies that the guest's own S2 must
      fit in the host's. This is odd, for multiple reasons:
      
      - the PARange values and the number of IPA bits don't necessarily
        match: you can have 33 bits of IPA space, and yet you can only
        describe 32 or 36 bits of PARange
      
      - When userspace set the IPA space, it creates a contract with the
        kernel saying "this is the IPA space I'm prepared to handle".
        At no point does it constraint the guest's own IPA space as
        long as the guest doesn't try to use a [I]PA outside of the
        IPA space set by userspace
      
      - We don't even try to hide the value of ID_AA64MMFR0_EL1.PARange.
      
      And then there is the consequence of the above: if a guest tries
      to create a S2 that has for input address something that is larger
      than the IPA space defined by the host, we inject a fatal exception.
      
      This is no good. For all intent and purposes, a guest should be
      able to have the S2 it really wants, as long as the *output* address
      of that S2 isn't outside of the IPA space.
      
      For that, we need to have a per-s2_mmu VTCR_EL2 setting, which
      allows us to represent the full PARange. Move the vctr field into
      the s2_mmu structure, which has no impact whatsoever, except for NV.
      
      Note that once we are able to override ID_AA64MMFR0_EL1.PARange
      from userspace, we'll also be able to restrict the size of the
      shadow S2 that NV uses.
      Signed-off-by: default avatarMarc Zyngier <maz@kernel.org>
      Link: https://lore.kernel.org/r/20231012205108.3937270-1-maz@kernel.orgSigned-off-by: default avatarOliver Upton <oliver.upton@linux.dev>
      fe49fd94
  5. 20 Oct, 2023 5 commits
  6. 05 Oct, 2023 3 commits
  7. 30 Sep, 2023 1 commit
  8. 24 Sep, 2023 4 commits
    • Linus Torvalds's avatar
      Linux 6.6-rc3 · 6465e260
      Linus Torvalds authored
      6465e260
    • Linus Torvalds's avatar
      Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm · 8a511e7e
      Linus Torvalds authored
      Pull kvm fixes from Paolo Bonzini:
      "ARM:
      
         - Fix EL2 Stage-1 MMIO mappings where a random address was used
      
         - Fix SMCCC function number comparison when the SVE hint is set
      
        RISC-V:
      
         - Fix KVM_GET_REG_LIST API for ISA_EXT registers
      
         - Fix reading ISA_EXT register of a missing extension
      
         - Fix ISA_EXT register handling in get-reg-list test
      
         - Fix filtering of AIA registers in get-reg-list test
      
        x86:
      
         - Fixes for TSC_AUX virtualization
      
         - Stop zapping page tables asynchronously, since we don't zap them as
           often as before"
      
      * tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm:
        KVM: SVM: Do not use user return MSR support for virtualized TSC_AUX
        KVM: SVM: Fix TSC_AUX virtualization setup
        KVM: SVM: INTERCEPT_RDTSCP is never intercepted anyway
        KVM: x86/mmu: Stop zapping invalidated TDP MMU roots asynchronously
        KVM: x86/mmu: Do not filter address spaces in for_each_tdp_mmu_root_yield_safe()
        KVM: x86/mmu: Open code leaf invalidation from mmu_notifier
        KVM: riscv: selftests: Selectively filter-out AIA registers
        KVM: riscv: selftests: Fix ISA_EXT register handling in get-reg-list
        RISC-V: KVM: Fix riscv_vcpu_get_isa_ext_single() for missing extensions
        RISC-V: KVM: Fix KVM_GET_REG_LIST API for ISA_EXT registers
        KVM: selftests: Assert that vasprintf() is successful
        KVM: arm64: nvhe: Ignore SVE hint in SMCCC function ID
        KVM: arm64: Properly return allocated EL2 VA from hyp_alloc_private_va_range()
      8a511e7e
    • Linus Torvalds's avatar
      Merge tag 'trace-v6.6-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/trace/linux-trace · 5edc6bb3
      Linus Torvalds authored
      Pull tracing fixes from Steven Rostedt:
      
       - Fix the "bytes" output of the per_cpu stat file
      
         The tracefs/per_cpu/cpu*/stats "bytes" was giving bogus values as the
         accounting was not accurate. It is suppose to show how many used
         bytes are still in the ring buffer, but even when the ring buffer was
         empty it would still show there were bytes used.
      
       - Fix a bug in eventfs where reading a dynamic event directory (open)
         and then creating a dynamic event that goes into that diretory screws
         up the accounting.
      
         On close, the newly created event dentry will get a "dput" without
         ever having a "dget" done for it. The fix is to allocate an array on
         dir open to save what dentries were actually "dget" on, and what ones
         to "dput" on close.
      
      * tag 'trace-v6.6-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/trace/linux-trace:
        eventfs: Remember what dentries were created on dir open
        ring-buffer: Fix bytes info in per_cpu buffer stats
      5edc6bb3
    • Linus Torvalds's avatar
      Merge tag 'cxl-fixes-6.6-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl · 2ad78f8c
      Linus Torvalds authored
      Pull cxl fixes from Dan Williams:
       "A collection of regression fixes, bug fixes, and some small cleanups
        to the Compute Express Link code.
      
        The regressions arrived in the v6.5 dev cycle and missed the v6.6
        merge window due to my personal absences this cycle. The most
        important fixes are for scenarios where the CXL subsystem fails to
        parse valid region configurations established by platform firmware.
        This is important because agreement between OS and BIOS on the CXL
        configuration is fundamental to implementing "OS native" error
        handling, i.e. address translation and component failure
        identification.
      
        Other important fixes are a driver load error when the BIOS lets the
        Linux PCI core handle AER events, but not CXL memory errors.
      
        The other fixex might have end user impact, but for now are only known
        to trigger in our test/emulation environment.
      
        Summary:
      
         - Fix multiple scenarios where platform firmware defined regions fail
           to be assembled by the CXL core.
      
         - Fix a spurious driver-load failure on platforms that enable OS
           native AER, but not OS native CXL error handling.
      
         - Fix a regression detecting "poison" commands when "security"
           commands are also defined.
      
         - Fix a cxl_test regression with the move to centralize CXL port
           register enumeration in the CXL core.
      
         - Miscellaneous small fixes and cleanups"
      
      * tag 'cxl-fixes-6.6-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl:
        cxl/acpi: Annotate struct cxl_cxims_data with __counted_by
        cxl/port: Fix cxl_test register enumeration regression
        cxl/region: Refactor granularity select in cxl_port_setup_targets()
        cxl/region: Match auto-discovered region decoders by HPA range
        cxl/mbox: Fix CEL logic for poison and security commands
        cxl/pci: Replace host_bridge->native_aer with pcie_aer_is_native()
        PCI/AER: Export pcie_aer_is_native()
        cxl/pci: Fix appropriate checking for _OSC while handling CXL RAS registers
      2ad78f8c
  9. 23 Sep, 2023 9 commits