- 28 May, 2024 14 commits
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Raymond Hackley authored
Core Prime LTE uses ST LIS2HH12 accelerometer. Add support for it. [Stephen: Use common &st_accel definition from common dtsi] Signed-off-by:
Stephan Gerhold <stephan@gerhold.net> Signed-off-by:
Raymond Hackley <raymondhackley@protonmail.com> Link: https://lore.kernel.org/r/20240406111348.14358-4-raymondhackley@protonmail.comSigned-off-by:
Bjorn Andersson <andersson@kernel.org>
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Siddharth Manthan authored
Some Grand Prime use a ST LSM303C accelerometer/magnetometer combo. Add support for it. Signed-off-by:
Siddharth Manthan <siddharth.manthan@gmail.com> [Stephan: Move sensors to common dtsi (disabled by default)] Signed-off-by:
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Joe Mason authored
Some Grand Prime use a Bosch BMC150 accelerometer/magnetometer combo. The chip provides two separate I2C devices for the accelerometer and magnetometer that are already supported by the bmc150-accel and bmc150-magn driver. Signed-off-by:
Joe Mason <buddyjojo06@outlook.com> [Stephan: Move sensors to common dtsi, disabled by default] Signed-off-by:
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Nikita Travkin authored
Add compatible values for the msm8916 based Motorola smartphones. Signed-off-by:
Nikita Travkin <nikita@trvn.ru> Acked-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240405-msm8916-moto-init-v1-1-502b58176d34@trvn.ruSigned-off-by:
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Gianluca Boiano authored
This node is actually found on some msm8953 devices (xiaomi-mido) and allows irled enablement Signed-off-by:
Gianluca Boiano <morf3089@gmail.com> Reviewed-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240402-pmi8950-pwm-support-v1-2-1a66899eeeb3@gmail.comSigned-off-by:
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Neil Armstrong authored
This documents Lenovo Smart Tab M10 (WiFi) (model tbx605f) which is a 10.1" tablet by Lenovo based on the SDM450 SoC. Signed-off-by:
Neil Armstrong <neil.armstrong@linaro.org> Acked-by:
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Sumit Garg authored
Add Schneider Electric HMIBSC board DTS. The HMIBSC board is an IIoT Edge Box Core board based on the Qualcomm APQ8016E SoC. Support for Schneider Electric HMIBSC. Features: - Qualcomm Snapdragon 410C SoC - APQ8016 (4xCortex A53, Adreno 306) - 1GiB RAM - 8GiB eMMC, SD slot - WiFi and Bluetooth - 2x Host, 1x Device USB port - HDMI - Discrete TPM2 chip over SPI - USB ethernet adaptors (soldered) Co-developed-by:
Jagdish Gediya <jagdish.gediya@linaro.org> Signed-off-by:
Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by:
Sumit Garg <sumit.garg@linaro.org> Link: https://lore.kernel.org/r/20240527053826.294526-4-sumit.garg@linaro.orgSigned-off-by:
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Sumit Garg authored
Document the compatible for the Schneider Electric HMIBSC IIoT edge box core board based on the Qualcomm APQ8016E SoC. Acked-by:
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Sumit Garg authored
Add vendor prefix for Schneider Electric (https://www.se.com/). Acked-by:
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Dmitry Baryshkov authored
There is no need to mention and/or to touch in any way the intermediate (source) clocks. Drop them from MSM8996 UFSHCD schema, making it follow the example lead by all other platforms. Reviewed-by:
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240408-msm8996-fix-ufs-v4-4-ee1a28bf8579@linaro.orgSigned-off-by:
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Dmitry Baryshkov authored
Instead of setting the frequency of the interim UFS_ICE_CORE_CLK_SRC clock, set the frequency of the leaf GCC_UFS_ICE_CORE_CLK clock directly. Reviewed-by:
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Dmitry Baryshkov authored
Follow the example of other platforms and specify core_clk frequencies in the frequency table in addition to the core_clk_src frequencies. The driver should be setting the leaf frequency instead of some interim clock freq. Suggested-by:
Nitin Rawat <quic_nitirawa@quicinc.com> Fixes: 57fc67ef ("arm64: dts: qcom: msm8996: Add ufs related nodes") Reviewed-by:
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Srinivas Kandagatla authored
The ADSP provides fastrpc/compute capabilities. Enable support for the fastrpc on this DSP. Signed-off-by:
Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by:
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Dmitry Baryshkov authored
MSM8996 provides limited glink support, so add corresponding device tree nodes. For example the following interfaces are provided on db820c: modem: 2080000.remoteproc:glink-edge.LOOPBACK_CTL_MPSS.-1.-1 2080000.remoteproc:glink-edge.glink_ssr.-1.-1 2080000.remoteproc:glink-edge.rpmsg_chrdev.0.0 adsp: 9300000.remoteproc:glink-edge.LOOPBACK_CTL_LPASS.-1.-1 9300000.remoteproc:glink-edge.glink_ssr.-1.-1 9300000.remoteproc:glink-edge.rpmsg_chrdev.0.0 Reviewed-by:
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- 27 May, 2024 26 commits
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Gabor Juhos authored
Add device tree source for the TP-Link Archer AX55 v1 [1] which is a dual-band WiFi router based on the IPQ5018 SoC. At the moment, only the UART, the GPIO LEDs and buttons are usable, but it makes it possible to boot an initramfs image on the device. The device tree can be extended in the future, once support for other periherals will be available for the platform. 1. https://www.tp-link.com/en/home-networking/wifi-router/archer-ax55/v1/Signed-off-by:
Gabor Juhos <j4g8y7@gmail.com> Link: https://lore.kernel.org/r/20240326-archer-ax55-v1-v4-2-dc5b54a4bb00@gmail.comSigned-off-by:
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Gabor Juhos authored
Document the TP-Link Archer AX55 v1 which is a dual-band WiFi router based on the IPQ5018 SoC. Signed-off-by:
Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20240326-archer-ax55-v1-v4-1-dc5b54a4bb00@gmail.comSigned-off-by:
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Luca Weiss authored
Add the compatible for this Samsung smartphone ("phablet" as it was named in that era). Acked-by:Luca Weiss <luca@z3ntu.xyz> Link: https://lore.kernel.org/r/20240314-samsung-hlte-v2-1-84094b41c033@z3ntu.xyzSigned-off-by:
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Mrinmay Sarkar authored
The PCIe EP controller on SA8775P supports cache coherency, hence add the "dma-coherent" property to mark it as such. Signed-off-by:
Mrinmay Sarkar <quic_msarkar@quicinc.com> Reviewed-by:
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Bryant Mairs authored
Add binding documentation for Samsung Galaxy Tab 4 8.0 Wi-Fi tablet which is based on Snapdragon 400 (apq8026) SoC. Acked-by:
Linus Walleij <linus.walleij@linaro.org> Acked-by:
Bryant Mairs <bryant@mai.rs> Link: https://lore.kernel.org/r/20240219214643.197116-2-bryant@mai.rsSigned-off-by:
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Alexandru Gagniuc authored
The IPQ95xx uses an IPQ4019 compatible MDIO controller that is already supported. Add a DT node to expose it. Signed-off-by:
Alexandru Gagniuc <mr.nuke.me@gmail.com> Link: https://lore.kernel.org/r/20240507024758.2810514-2-mr.nuke.me@gmail.comSigned-off-by:
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Adam Skladowski authored
Add node describing wireless connectivity subsystem. Signed-off-by:
Adam Skladowski <a39.skl@gmail.com> Link: https://lore.kernel.org/r/20240508163455.8757-5-a39.skl@gmail.comSigned-off-by:
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Adam Skladowski authored
Add Adreno GPU node. Signed-off-by:
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Adam Skladowski authored
Add MDSS nodes to support displays on MSM8976 SoC. Signed-off-by:
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Adam Skladowski authored
Add the nodes describing the apps and gpu iommu and its context banks that are found on msm8976 SoCs. Signed-off-by:
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Luca Weiss authored
Add the different services found on APR on some devices with SC7280 SoC. Additionally add an empty sound node in the root node as is seen on other SoC dtsi files so device dt's can easily use that. Signed-off-by:
Luca Weiss <luca.weiss@fairphone.com> Link: https://lore.kernel.org/r/20240510-sc7280-apr-v1-1-e9eabda05f85@fairphone.comSigned-off-by:
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Dmitry Baryshkov authored
Follow other Qualcomm platforms and rename pm8150b_role_switch_in to pm8150_hs_in. Corresponding port is described as HS port rather than role switching. Signed-off-by:
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Dmitry Baryshkov authored
Follow example of other platforms. Rename HS graph nodes to contain 'dwc3_hs' and link SS lanes from DWC3 controllers to QMP PHYs. Signed-off-by:
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Dmitry Baryshkov authored
Follow example of other platforms. Rename HS graph nodes to contain 'dwc3_hs' and link SS lanes from DWC3 controllers to QMP PHYs. Signed-off-by:
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Dmitry Baryshkov authored
Follow example of other platforms. Rename HS graph nodes to contain 'dwc3_hs' and link SS lanes from DWC3 controllers to QMP PHYs. Signed-off-by:
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Dmitry Baryshkov authored
To follow other Qualcomm platforms, update QMP USB+DP PHYs to use newer bindings rather than old bindings which had PHYs as subdevices. Signed-off-by:
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Dmitry Baryshkov authored
The SuperSpeed signals originate from the DWC3 host controller and then are routed through the Combo QMP PHY, where they are multiplexed with the DisplayPort signals. Add corresponding OF graph link. Reported-by:
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Dmitry Baryshkov authored
The OF graph should describe physical signals. There is no 'role switch' signal between Type-C connector and the DWC3 USB controller. Rename endpoints to mention USB HS signal instead (this follows the example lead by other plaforms, including QRB2210 RB1, QRB4210 RB2 and all PMIC GLINK platforms). Reviewed-by:
Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by:
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Dmitry Baryshkov authored
Correct the clocks being used by the display clock controller on the SC8180X platform (to match the schema): - Drop the sleep clock - Add DSI clocks - Reorder eDP / DP clocks This changes the order of clocks, however it should be noted that the clock list was neither correct nor followed the schema beforehand. Signed-off-by:
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Marc Gonzalez authored
15 qcom platform DTSI files define an adreno_smmu node. msm8998 is the only one with adreno_smmu disabled by default. There's no reason why this SMMU should be disabled by default, it doesn't need any further configuration. Bring msm8998 in line with the 14 other platforms. This fixes GPU init failing with ENODEV: msm_dpu c901000.display-controller: failed to load adreno gpu msm_dpu c901000.display-controller: failed to bind 5000000.gpu (ops a3xx_ops): -19 Fixes: 87cd46d6 ("Configure Adreno GPU and related IOMMU") Signed-off-by:
Marc Gonzalez <mgonzalez@freebox.fr> Reviewed-by:
Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by:
Jeffrey Hugo <quic_jhugo@quicinc.com> Link: https://lore.kernel.org/r/be51d1a4-e8fc-48d1-9afb-a42b1d6ca478@freebox.frSigned-off-by:
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Rohit Agarwal authored
Add devicetree node for I2C and SPI busses in SDX75. Signed-off-by:
Rohit Agarwal <rohiagar@qti.qualcomm.com> Link: https://lore.kernel.org/r/20240517100423.2006022-3-quic_rohiagar@quicinc.comSigned-off-by:
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Jie Gan authored
Add following coresight components on SA8775p, TMC/ETF, TPDM, dynamic Funnel, TPDA and ETM. Signed-off-by:
Jie Gan <quic_jiegan@quicinc.com> Link: https://lore.kernel.org/r/20240521011946.3148712-2-quic_jiegan@quicinc.comSigned-off-by:
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Neil Armstrong authored
This add initial support for the Lenovo Smart Tab M10 (WiFi) (model tbx605f) which is a 10.1" tablet by Lenovo based on the SDM450 SoC. It has a 10.1" LCP touch panel, SDCard slot, Volume+Power buttons, USB-C port amd front-facing camera (not supported). The proper LCP Panel support will be added later, for now using the simeple-framebuffer with the bootloader-initialized video memory. Signed-off-by:
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Naina Mehta authored
Enable SDHCI on sdx75-idp to support SD card. Also add the required regulators. Signed-off-by:
Naina Mehta <quic_nainmeht@quicinc.com> Link: https://lore.kernel.org/r/20240523120337.9530-4-quic_nainmeht@quicinc.comSigned-off-by:
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Naina Mehta authored
Add sdhc node for SDX75 SoC to support SD card. Also add pins required for SDHCI. Signed-off-by:
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Richard Acayan authored
The shared memory region is used for information about the SoC and communication with remote processors. Add the smem region for SDM670. Signed-off-by:
Richard Acayan <mailingradian@gmail.com> Link: https://lore.kernel.org/r/20240524012023.318965-8-mailingradian@gmail.comSigned-off-by:
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