1. 09 Mar, 2020 10 commits
    • Martin Leung's avatar
      drm/amd/display: writing stereo polarity register if swapped · e592e85f
      Martin Leung authored
      [why]
      on some displays that prefer swapped polarity we were seeing L/R images
      swapped because OTG_STEREO_SYNC_OUTPUT_POLARITY would always be mapped
      to 0
      
      [how]
      fix initial dal3 implementation to properly update the polarity field
      according to the crtc_stereo_flags (same as
      OTG_STEREO_EYE_FLAG_POLARITY)
      Signed-off-by: default avatarMartin Leung <martin.leung@amd.com>
      Reviewed-by: default avatarAric Cyr <Aric.Cyr@amd.com>
      Acked-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
      Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
      e592e85f
    • Rodrigo Siqueira's avatar
      drm/amd/display: Stop if retimer is not available · a0e40018
      Rodrigo Siqueira authored
      Raven provides retimer feature support that requires i2c interaction in
      order to make it work well, all settings required for this configuration
      are loaded from the Atom bios which include the i2c address. If the
      retimer feature is not available, we should abort the attempt to set
      this feature, otherwise, it makes the following line return
      I2C_CHANNEL_OPERATION_NO_RESPONSE:
      
       i2c_success = i2c_write(pipe_ctx, slave_address, buffer, sizeof(buffer));
       ...
       if (!i2c_success)
         ASSERT(i2c_success);
      
      This ends up causing problems with hotplugging HDMI displays on Raven,
      and causes retimer settings to warn like so:
      
      WARNING: CPU: 1 PID: 429 at
      drivers/gpu/drm/amd/amdgpu/../dal/dc/core/dc_link.c:1998
      write_i2c_retimer_setting+0xc2/0x3c0 [amdgpu] Modules linked in:
      edac_mce_amd ccp kvm irqbypass binfmt_misc crct10dif_pclmul crc32_pclmul
      ghash_clmulni_intel snd_hda_codec_realtek snd_hda_codec_generic
      ledtrig_audio snd_hda_codec_hdmi snd_hda_intel amdgpu(+) snd_hda_codec
      snd_hda_core snd_hwdep snd_pcm snd_seq_midi snd_seq_midi_event
      snd_rawmidi aesni_intel snd_seq amd_iommu_v2 gpu_sched aes_x86_64
      crypto_simd cryptd glue_helper snd_seq_device ttm drm_kms_helper
      snd_timer eeepc_wmi wmi_bmof asus_wmi sparse_keymap drm mxm_wmi snd
      k10temp fb_sys_fops syscopyarea sysfillrect sysimgblt soundcore joydev
      input_leds mac_hid sch_fq_codel parport_pc ppdev lp parport ip_tables
      x_tables autofs4 igb i2c_algo_bit hid_generic usbhid i2c_piix4 dca ahci
      hid libahci video wmi gpio_amdpt gpio_generic CPU: 1 PID: 429 Comm:
      systemd-udevd Tainted: G        W         5.2.0-rc1sept162019+ #1
      Hardware name: System manufacturer System Product Name/ROG STRIX B450-F
      GAMING, BIOS 2605 08/06/2019
      RIP: 0010:write_i2c_retimer_setting+0xc2/0x3c0 [amdgpu]
      Code: ff 0f b6 4d ce 44 0f b6 45 cf 44 0f b6 c8 45 89 cf 44 89 e2 48 c7
      c6 f0 34 bc c0 bf 04 00 00 00 e8 63 b0 90 ff 45 84 ff 75 02 <0f> 0b 42
      0f b6 04 73 8d 50 f6 80 fa 02 77 8c 3c 0a 0f 85 c8 00 00 RSP:
      0018:ffffa99d02726fd0 EFLAGS: 00010246
      RAX: 0000000000000000 RBX: ffffa99d02727035 RCX: 0000000000000006
      RDX: 0000000000000000 RSI: 0000000000000002 RDI: ffff976acc857440
      RBP: ffffa99d02727018 R08: 0000000000000002 R09: 000000000002a600
      R10: ffffe90610193680 R11: 00000000000005e3 R12: 000000000000005d
      R13: ffff976ac4b201b8 R14: 0000000000000001 R15: 0000000000000000
      FS:  00007f14f99e1680(0000) GS:ffff976acc840000(0000) knlGS:0000000000000000
      CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
      CR2: 00007fdf212843b8 CR3: 0000000408906000 CR4: 00000000003406e0
      Call Trace:
       core_link_enable_stream+0x626/0x680 [amdgpu]
       dce110_apply_ctx_to_hw+0x414/0x4e0 [amdgpu]
       dc_commit_state+0x331/0x5e0 [amdgpu]
       ? drm_calc_timestamping_constants+0xf9/0x150 [drm]
       amdgpu_dm_atomic_commit_tail+0x395/0x1e00 [amdgpu]
       ? dm_plane_helper_prepare_fb+0x20c/0x280 [amdgpu]
       commit_tail+0x42/0x70 [drm_kms_helper]
       drm_atomic_helper_commit+0x10c/0x120 [drm_kms_helper]
       amdgpu_dm_atomic_commit+0x95/0xa0 [amdgpu]
       drm_atomic_commit+0x4a/0x50 [drm]
       restore_fbdev_mode_atomic+0x1c0/0x1e0 [drm_kms_helper]
       restore_fbdev_mode+0x4c/0x160 [drm_kms_helper]
       ? _cond_resched+0x19/0x40
       drm_fb_helper_restore_fbdev_mode_unlocked+0x4e/0xa0 [drm_kms_helper]
       drm_fb_helper_set_par+0x2d/0x50 [drm_kms_helper]
       fbcon_init+0x471/0x630
       visual_init+0xd5/0x130
       do_bind_con_driver+0x20a/0x430
       do_take_over_console+0x7d/0x1b0
       do_fbcon_takeover+0x5c/0xb0
       fbcon_event_notify+0x6cd/0x8a0
       notifier_call_chain+0x4c/0x70
       blocking_notifier_call_chain+0x43/0x60
       fb_notifier_call_chain+0x1b/0x20
       register_framebuffer+0x254/0x360
       __drm_fb_helper_initial_config_and_unlock+0x2c5/0x510 [drm_kms_helper]
       drm_fb_helper_initial_config+0x35/0x40 [drm_kms_helper]
       amdgpu_fbdev_init+0xcd/0x100 [amdgpu]
       amdgpu_device_init+0x1156/0x1930 [amdgpu]
       amdgpu_driver_load_kms+0x8d/0x2e0 [amdgpu]
       drm_dev_register+0x12b/0x1c0 [drm]
       amdgpu_pci_probe+0xd3/0x160 [amdgpu]
       local_pci_probe+0x47/0xa0
       pci_device_probe+0x142/0x1b0
       really_probe+0xf5/0x3d0
       driver_probe_device+0x11b/0x130
       device_driver_attach+0x58/0x60
       __driver_attach+0xa3/0x140
       ? device_driver_attach+0x60/0x60
       ? device_driver_attach+0x60/0x60
       bus_for_each_dev+0x74/0xb0
       ? kmem_cache_alloc_trace+0x1a3/0x1c0
       driver_attach+0x1e/0x20
       bus_add_driver+0x147/0x220
       ? 0xffffffffc0cb9000
       driver_register+0x60/0x100
       ? 0xffffffffc0cb9000
       __pci_register_driver+0x5a/0x60
       amdgpu_init+0x74/0x83 [amdgpu]
       do_one_initcall+0x4a/0x1fa
       ? _cond_resched+0x19/0x40
       ? kmem_cache_alloc_trace+0x3f/0x1c0
       ? __vunmap+0x1cc/0x200
       do_init_module+0x5f/0x227
       load_module+0x2330/0x2b40
       __do_sys_finit_module+0xfc/0x120
       ? __do_sys_finit_module+0xfc/0x120
       __x64_sys_finit_module+0x1a/0x20
       do_syscall_64+0x5a/0x130
       entry_SYSCALL_64_after_hwframe+0x44/0xa9
      RIP: 0033:0x7f14f9500839
      Code: 00 f3 c3 66 2e 0f 1f 84 00 00 00 00 00 0f 1f 40 00 48 89 f8 48 89
      f7 48 89 d6 48 89 ca 4d 89 c2 4d 89 c8 4c 8b 4c 24 08 0f 05 <48> 3d 01
      f0 ff ff 73 01 c3 48 8b 0d 1f f6 2c 00 f7 d8 64 89 01 48
      RSP: 002b:00007fff9bc4f5a8 EFLAGS: 00000246 ORIG_RAX: 0000000000000139
      RAX: ffffffffffffffda RBX: 000055afb5abce30 RCX: 00007f14f9500839
      RDX: 0000000000000000 RSI: 000055afb5ace0f0 RDI: 0000000000000017
      RBP: 000055afb5ace0f0 R08: 0000000000000000 R09: 000000000000000a
      R10: 0000000000000017 R11: 0000000000000246 R12: 0000000000000000
      R13: 000055afb5aad800 R14: 0000000000020000 R15: 0000000000000000
      ---[ end trace c286e96563966f08 ]---
      
      This commit reworks the way that we handle i2c write for retimer in the
      way that we abort this configuration if the feature is not available in
      the device. For debug sake, we kept a simple log message in case the
      retimer is not available.
      Signed-off-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
      Reviewed-by: default avatarHersen Wu <hersenxs.wu@amd.com>
      Acked-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
      Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
      a0e40018
    • Wenjing Liu's avatar
      drm/amd/display: fix a minor HDCP logging error · 1450d237
      Wenjing Liu authored
      [why]
      In HDCP Uninitialzed State, a CPIRQ event would cause log output
      internal policy error because the CPIRQ event is not recognized as
      unexpected event.
      
      [how]
      CPIRQ is issued in HDCP uninitialized state is unexpected.  We should
      set unexpected event flag in event ctx.
      Signed-off-by: default avatarWenjing Liu <Wenjing.Liu@amd.com>
      Reviewed-by: default avatarAshley Thomas <Ashley.Thomas2@amd.com>
      Acked-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
      Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
      1450d237
    • Wenjing Liu's avatar
      drm/amd/display: determine rx id list bytes to read based on device count · d7ecf5e3
      Wenjing Liu authored
      [why]
      Some RX doesn't like us to read rx id list upto max rx id list size.  As
      discussed, we decided to read rx id list based on device count.
      
      [how]
      According to HDCP specs the actual size of rx id list is calculated as
      rx id list size = 2+3+16+5*device_count.  We will read 16 bytes at a
      time until it reached or exceeded rx id list size.
      Signed-off-by: default avatarWenjing Liu <Wenjing.Liu@amd.com>
      Reviewed-by: default avatarAshley Thomas <Ashley.Thomas2@amd.com>
      Acked-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
      Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
      d7ecf5e3
    • Nikola Cornij's avatar
      drm/amd/display: Program DSC during timing programming · 8cc426d7
      Nikola Cornij authored
      [why]
      Link or DIG BE can't be exposed to a higher stream bandwidth than they
      can handle. When DSC is required to fit the stream into the link
      bandwidth, DSC has to be programmed during timing programming to ensure
      this. Without it, intermittent issues such as black screen after S3 or a
      hot-plug can be seen.
      
      [how]
      Move DSC programming from enabling stream on link to timing setup.
      Signed-off-by: default avatarNikola Cornij <nikola.cornij@amd.com>
      Reviewed-by: default avatarTony Cheng <Tony.Cheng@amd.com>
      Acked-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
      Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
      8cc426d7
    • Yongqiang Sun's avatar
      drm/amd/display: Not check wm and clk change flag in optimized bandwidth. · 4c631826
      Yongqiang Sun authored
      [Why]
      System isn't able to enter S0i3 due to not send display count 0 to smu.
      When dpms off, clk changed flag is cleared alreay, and it is checked
      when doing optimized bandwidth, and update clocks is bypassed due to the
      flag is unset.
      
      [How]
      Remove check flag incide the function since watermark values and clocks
      values are checked during update to determine whether to perform it, no
      need to check it again outside the function.
      Signed-off-by: default avatarYongqiang Sun <yongqiang.sun@amd.com>
      Reviewed-by: default avatarTony Cheng <Tony.Cheng@amd.com>
      Acked-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
      Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
      4c631826
    • Braden Bakker's avatar
      drm/amd/display: Add registry for mem pwr control · cc493508
      Braden Bakker authored
      [What]
      Need debug options to control lightl/deep sleep
      [How]
      Add registry for memory power control
      Signed-off-by: default avatarBraden Bakker <Braden.Bakker@amd.com>
      Reviewed-by: default avatarCharlene Liu <Charlene.Liu@amd.com>
      Acked-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
      Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
      cc493508
    • Wenjing Liu's avatar
      drm/amd/display: determine is mst hdcp based on stream instead of sink signal · b6a1a0e7
      Wenjing Liu authored
      [why]
      It is possible even if sink signal is MST but driver enables SST stream.
      We should not determine if we should do MST authentication based on
      sink's capability.
      Instead we should determine whether to do MST authentication based on
      what we have enabled in stream.
      Signed-off-by: default avatarWenjing Liu <Wenjing.Liu@amd.com>
      Reviewed-by: default avatarAshley Thomas <Ashley.Thomas2@amd.com>
      Acked-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
      Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
      b6a1a0e7
    • Isabel Zhang's avatar
      drm/amd/display: Add stay count and bstatus to HDCP log · caa08c58
      Isabel Zhang authored
      [Why]
      So the values of stay count and bstatus can be easily viewed during
      debugging.
      
      [How]
      Add stay count and bstatus values to be outputted in HDCP log
      Signed-off-by: default avatarIsabel Zhang <isabel.zhang@amd.com>
      Reviewed-by: default avatarWenjing Liu <Wenjing.Liu@amd.com>
      Acked-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
      Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
      caa08c58
    • Martin Leung's avatar
      drm/amd/display: update soc bb for nv14 · e1ab4a91
      Martin Leung authored
      [why]
      nv14 previously inherited soc bb from generic dcn 2, did not match
      watermark values according to memory team
      
      [how]
      add nv14 specific soc bb: copy nv2 generic that it was
      using from before, but changed num channels to 8
      Signed-off-by: default avatarMartin Leung <martin.leung@amd.com>
      Reviewed-by: default avatarJun Lei <Jun.Lei@amd.com>
      Acked-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
      Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
      e1ab4a91
  2. 06 Mar, 2020 18 commits
  3. 05 Mar, 2020 12 commits