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  1. 20 Aug, 2007 10 commits
  3. 19 Aug, 2007 1 commit
  5. 18 Aug, 2007 25 commits
  7. 17 Aug, 2007 4 commits
    • Thomas Renninger's avatar
      Cross-compilation between e.g. i386 -> 64bit could break -> work around it · 11814208
      Thomas Renninger authored 
      Adrian Bunk: scripts/mod/file2alias.c is compiled with HOSTCC and ensures that
kernel_ulong_t is correct, but it can't cope with different padding on
different architectures.
Signed-off-by: default avatarThomas Renninger <trenn@suse.de>
Signed-off-by: default avatarTony Luck <tony.luck@intel.com>
      11814208
    • Peter Chubb's avatar
      [IA64] Enable early console for Ski simulator · 471e7a44
      Peter Chubb authored 
      When using Ski to debug early startup, it's a bit of a pain not to
have printk.

This patch enables the simulated console very early.
It may be worth conditionalising on the command line... but this is
enough for now.
Signed-off-by: default avatarPeter Chubb <peterc@gelato.unsw.edu.au>
Signed-off-by: default avatarTony Luck <tony.luck@intel.com>
      471e7a44
    • Shaohua Li's avatar
      [IA64] forbid ptrace changes psr.ri to 3 · b09e789c
      Shaohua Li authored 
      The "ri" field in the processor status register only has defined
values of 0, 1, 2.  Do not let ptrace set this to 3.  As with
other reserved fields in registers we silently discard the value.
Signed-off-by: default avatarShaohua Li <shaohua.li@intel.com>
Signed-off-by: default avatarTony Luck <tony.luck@intel.com>
      b09e789c
    • David S. Miller's avatar
      [MATH-EMU]: Fix underflow exception reporting. · 40584961
      David S. Miller authored 
      The underflow exception cases were wrong.

This is one weird area of ieee1754 handling in that the underflow
behavior changes based upon whether underflow is enabled in the trap
enable mask of the FPU control register.  As a specific case the Sparc
V9 manual gives us the following description:

--------------------
If UFM = 0:     Underflow occurs if a nonzero result is tiny and a
                loss of accuracy occurs.  Tininess may be detected
                before or after rounding.  Loss of accuracy may be
                either a denormalization loss or an inexact result.

If UFM = 1:     Underflow occurs if a nonzero result is tiny.
                Tininess may be detected before or after rounding.
--------------------

What this amounts to in the packing case is if we go subnormal,
we set underflow if any of the following are true:

1) rounding sets inexact
2) we ended up rounding back up to normal (this is the case where
   we set the exponent to 1 and set the fraction to zero), this
   should set inexact too
3) underflow is set in FPU control register trap-enable mask

The initially discovered example was "DBL_MIN / 16.0" which
incorrectly generated an underflow.  It should not, unless underflow
is set in the trap-enable mask of the FPU csr.

Another example, "0x0.0000000000001p-1022 / 16.0", should signal both
inexact and underflow.  The cpu implementations and ieee1754
literature is very clear about this.  This is case #2 above.

However, if underflow is set in the trap enable mask, only underflow
should be set and reported as a trap.  That is handled properly by the
prioritization logic in

arch/sparc{,64}/math-emu/math.c:record_exception().

Based upon a report and test case from Jakub Jelinek.
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      40584961
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