1. 20 Sep, 2022 35 commits
  2. 19 Sep, 2022 4 commits
  3. 17 Sep, 2022 1 commit
    • David S. Miller's avatar
      Merge branch 'octeontx2-cn10k-ptp' · 44a8535f
      David S. Miller authored
      From: Naveen Mamindlapalli <naveenm@marvell.com>
      To: <kuba@kernel.org>, <davem@davemloft.net>, <edumazet@google.com>,
      	<pabeni@redhat.com>, <richardcochran@gmail.com>,
      	<netdev@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
      	<sgoutham@marvell.com>, <hkelam@marvell.com>
      Cc: Naveen Mamindlapalli <naveenm@marvell.com>
      Subject: [net-next PATCH 0/4] Add PTP support for CN10K silicon
      Date: Sat, 10 Sep 2022 13:24:12 +0530	[thread overview]
      Message-ID: <20220910075416.22887-1-naveenm@marvell.com> (raw)
      
      This patchset adds PTP support for CN10K silicon, specifically
      to workaround few hardware issues and to add 1-step mode.
      
      Patchset overview:
      
      Patch #1 returns correct ptp timestamp in nanoseconds captured
               when external timestamp event occurs.
      
      Patch #2 adds 1-step mode support.
      
      Patch #3 implements software workaround to generate PPS output properly.
      
      Patch #4 provides a software workaround for the rollover register default
               value, which causes ptp to return the wrong timestamp.
      ====================
      Acked-by: default avatarRichard Cochran <richardcochran@gmail.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      44a8535f