- 15 Oct, 2009 7 commits
-
-
Zhao Yakui authored
Sometimes we will get the incorrect display modeline when parsing the detailed timing in EDID. For example: >hsync/vsync width is zero >sync is beyond the blank. So add the basic check for the detailed timing in EDID to avoid the incorrect display modeline. Signed-off-by:
Zhao Yakui <yakui.zhao@intel.com> Signed-off-by:
Dave Airlie <airlied@redhat.com>
-
Matt Turner authored
Signed-off-by:
Matt Turner <mattst88@gmail.com> Signed-off-by:
-
Alex Deucher authored
fixes fdo bug 24496 Signed-off-by:
Alex Deucher <alexdeucher@gmail.com> Signed-off-by:
-
Alex Deucher authored
D1MODE_INTERLEAVE_EN was getting set in some cases in the encoder quirks function due to the changes in 5a9bcaccSigned-off-by:
-
Alex Deucher authored
Based partly on a patch from Christian Koenig <deathsimple@vodafone.de> - fix several memory leaks in radeon_connector->edid handling - store edid in radeon_connector->edid in detect() or get_modes() - switch hdmi detect code to use radeon_connector->edid - add support for oem boards multiple connectors that share a ddc line. - short circuit lvds_detect() if have a stored edid Signed-off-by:
-
Alex Deucher authored
- crtc 0 routing was wrong - need to clear various timing bits in FP_GEN_CNTL - need to set FP_H/V2_SYNC_STRT_WID regs for crtc 1 Signed-off-by:
-
Alex Deucher authored
radeon_encoder->active_device defines the active routing between the encoder and connector. The encoder fixup and dpms functions need to know the active_device to function properly. Setting active_device in the prepare hook was too late in some cases. Signed-off-by:
-
- 12 Oct, 2009 12 commits
-
-
Alex Deucher authored
drm modes are objects with indentifiers. Make sure to preserve the mode id when copying mode params. Signed-off-by:
-
Dave Airlie authored
With the adjust table introduction, we need to fill out index before getting the table version. Signed-off-by: -
Dave Airlie authored
This reverts commit 49c458e5. It seems to have some side effects in the non-kms cases. Signed-off-by:
-
Alex Deucher authored
In case the system has bad native mode info but valid edid. Signed-off-by:
-
Alex Deucher authored
This reduces the number of mode format conversions needed and makes native panel mode support cleaner. Signed-off-by:
-
Alex Deucher authored
- clean up tv timing handling - unify SetCRTC_Timing and SetCRTC_UsingDTDTiming Signed-off-by:
-
Alex Deucher authored
DCE3+ has an AdjustDisplayPll that will adjust the pixel clock accordingly based on the encoder/transmitter to handle special hw requirements. Signed-off-by:
-
Alex Deucher authored
Based on recommendation from bios docs. Signed-off-by:
-
Alex Deucher authored
If the panel data is bogus this can lead to problems later when the hardware trys to set the mode. If the data is invalid, report LVDS as disconnected. Should fix fdo bug 24247. Signed-off-by:
-
Michel Dänzer authored
While investigating the cause of CRTC FIFO underruns, I noticed that when converting the memory bandwidth calculation from the userspace X driver code, an instance of '8.0' was apparently accidentally converted to '80'. Signed-off-by:
Michel Dänzer <daenzer@vmware.com> Signed-off-by:
-
Michel Dänzer authored
The hook may change the number of bytes per pixel being scanned out, which affects the CRTC memory bandwidth requirements. E.g. booting in 8bpp and then running X in 32bpp would result in the bandwidth requirements being underestimated for the latter and consequently in CRTC FIFO underruns causing visible artifacts with 3D intensive workloads. ATOM changes only compile-tested. Signed-off-by:
-
Dave Airlie authored
The fb binding might be happening in a subsequent crtc setup call. gets rid of some lut issues. Signed-off-by:
-
- 08 Oct, 2009 1 commit
-
-
Dave Airlie authored
Both r100/r600 had this wrong, use the macro to extract the register to relocate. Signed-off-by:
-
- 07 Oct, 2009 6 commits
-
-
Robert Noland authored
There is no need to assign vb before you know that space is available. [agd5f: adapted for kernel tree.] Signed-off-by:
-
Dave Airlie authored
This is just a cleanup of the list macro usage. Signed-off-by: -
Jerome Glisse authored
For AGP to work unmapped access must cover VRAM & AGP as AGP is treated like VRAM by the GPU (ie physical address). This patch properly setup the virtual memory system aperture to cover AGP if AGP is enabled. It seems that there is memory corruption after resume when using AGP (RV770 seems unaffected thought). Version 2 just fix merge issue with updated AGP fallback patch. Signed-off-by:
Jerome Glisse <jglisse@redhat.com> Signed-off-by:
-
Jerome Glisse authored
When GPU acceleration is not working with AGP try to fallback to non AGP GART (either PCI or PCIE GART). This should make KMS failure on AGP less painfull. We still need to find out what is wrong when AGP fails but at least user have a lot of more chances to get a working configuration with acceleration. This patch also cleanup R600/RV770 fallback path so they use same code as others asics. Version 2 factorize agp disabling logic to avoid code duplication and bugs. Signed-off-by:
-
Jerome Glisse authored
Bad generated header file leaded to use wrong register to check IRQ status and acknowledge them. Fix the header and use proper registers. Signed-off-by:
-
Roel Kluin authored
Duplicate bits set Signed-off-by:
Roel Kluin <roel.kluin@gmail.com> Signed-off-by:
-
- 06 Oct, 2009 2 commits
-
-
Dave Airlie authored
the global refcount wasn't being increased after the first reference. this caused an oops on unload on a multi-gpu card. Signed-off-by: -
Dave Airlie authored
The previous patches had some unwanted side effects, I've fixed the lack of 32bpp working, and fixed up 16bpp so it should also work. this also adds the interface to allow the driver to set a preferred console depth so for example low memory rn50 can set it to 8bpp. It also catches 24bpp on cards that can't do it and forces 32bpp. Tested on r100/r600/i945. Signed-off-by:
-
- 05 Oct, 2009 4 commits
-
-
Dave Airlie authored
This adds support for the setcmap api and fixes the 8bpp support at least on radeon hardware. It adds a new load_lut hook which can be called once the color map is setup. Signed-off-by: -
Dave Airlie authored
Also add single crtc for RN50 chips. changes in v2: fix vblank init to respect single crtc flag fix r100 mode bandwidth to respect single crtc flag Signed-off-by: -
Zhao Yakui authored
We can get the corresponding info by adding the boot option of "drm.debug= 0x07". But On some boxes it will print the following message many times in course of moving mouse. In such case the useful DRM debug info will be flushed. >[drm:drm_mode_cursor_ioctl], Avoid using the DRM_DEBUG_KMS in drm_mode_cursor_ioctl. Signed-off-by:
-
Alex Deucher authored
"Surround View" is an option in the system bios that enables the AMD IGP chip in conjunction with a discrete AMD card. However, since the IGP vbios is part of the system bios it is not accessible via the rom bar or the legacy vga location. When "Surround View" is enabled in the system bios, the system bios puts a copy of the IGP vbios image at the start of vram. This patch adds support for reading the vbios image out of vram on IGP cards. Signed-off-by:
-
- 01 Oct, 2009 8 commits
-
-
Jerome Glisse authored
Avivo hw have vblank interrupt in different place, fixes irq handling (especialy irq disabling while suspending or shuting down the module). Signed-off-by:
-
Jerome Glisse authored
R600 & RV770 family are all using atombios so remove dead code and print an error message if we fail to find a valid atombios. Signed-off-by:
-
Jerome Glisse authored
When acceleration doesn't work we should free associated memory and stop GPU block responsible for hardware acceleration so we don't waste resource or let think one component of the driver that a GPU feature is working/running while it doesn't actualy work. Signed-off-by:
-
Jerome Glisse authored
We were calling reset unconditionaly in the startup path this is bad we need to call GPU reset for a good reason as after reset the GPU is in unknown states. To avoid any more bad things to happen we now also unconditionaly reinitialize the GPU after reset. This patch fix few issues reported by different people regarding KMS & R6XX/RV7XX hw. Signed-off-by:
-
Jerome Glisse authored
This split write back buffer handling into 3 functions, wb_fini for cleanup, wb_enable/wb_disable for enabling/disabling write back used for suspend/resume. This should fix potential issue of letting the write back active before suspending. We need to allocate memory in wb_enable because we can only allocate once GART is running. Signed-off-by:
-
Jerome Glisse authored
This remove old init path and allow code cleanup, now all hw use the new init path, see top of radeon.h for description of this. Signed-off-by:
-
Jerome Glisse authored
New init path allow to simply asic initialization and make easier to trace what happen on each different asic. We are removing most callback. Do a massive RS600 register cleanup to clarify RS600 register, we are still bit fuzy on some register and waiting for more informations. I don't have hw to test, so this patch is a best effort to not break anythings and to try to improve things. Signed-off-by:
-
Jerome Glisse authored
Also cleanup register specific to RS690/RS740. Version 2 add missing header file for register, remove unecessary call to AGP function and fix an indentation bug. Signed-off-by:
-
