- 18 Feb, 2021 3 commits
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Gustavo A. R. Silva authored
Fix potential integer overflow by casting actual_calculated_clock_100hz to u64, in order to give the compiler complete information about the proper arithmetic to use. Notice that such variable is used in a context that expects an expression of type u64 (64 bits, unsigned) and the following expression is currently being evaluated using 32-bit arithmetic: actual_calculated_clock_100hz * post_divider Fixes: 7a03fdf6 ("drm/amd/display: fix 64bit division issue on 32bit OS") Addresses-Coverity-ID: 1501691 ("Unintentional integer overflow") Signed-off-by:
Gustavo A. R. Silva <gustavoars@kernel.org> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Nirmoy Das authored
Fixes: 9037246b ("drm/amd/display: Add sysfs interface for set/get srm") Signed-off-by:
Nirmoy Das <nirmoy.das@amd.com> Acked-by:
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Marek Olšák authored
This fixes incorrect TCC harvesting info reported to userspace. The impact was a very very tiny performance degradation (unnecessary GL2 cache flushes). Signed-off-by:
Marek Olšák <marek.olsak@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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- 09 Feb, 2021 37 commits
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Jiapeng Chong authored
Fix the following coccicheck warning: ./drivers/gpu/drm/radeon/rs690.c:190:6-35: WARNING: Comparison to bool. Reported-by:
Abaci Robot <abaci@linux.alibaba.com> Signed-off-by:
Jiapeng Chong <jiapeng.chong@linux.alibaba.com> Signed-off-by:
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Jiapeng Chong authored
Fix the following coccicheck warning: ./drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h:319:11-23: WARNING: Comparison to bool. Reported-by:
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Alex Deucher authored
This reverts commit 4a3dea89. This causes blank screens for some users. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1388 Cc: Alvin Lee <alvin.lee2@amd.com> Cc: Jun Lei <Jun.Lei@amd.com> Cc: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Reviewed-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by:
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Tian Tao authored
Remove NULL checks before vfree() to fix these warnings: drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:102:2-8: WARNING: NULL check before some freeing functions is not needed. Signed-off-by:
Tian Tao <tiantao6@hisilicon.com> Signed-off-by:
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Xiaojian Du authored
This patch is to make the error log more clear for fine grain tuning function, it covers Raven/Raven2/Picasso/Renoir/Vangogh. The fine grain tuning function uses the sysfs file -- pp_od_clk_voltage, but only when another sysfs file -- power_dpm_force_performance_level is switched to "manual" mode, it is allowed to access "pp_od_clk_voltage". Signed-off-by:
Xiaojian Du <Xiaojian.Du@amd.com> Acked-by:
Huang Rui <ray.huang@amd.com> Acked-by:
Kevin Wang <kevin1.wang@amd.com> Signed-off-by:
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Jiawei Gu authored
Extend retry times of KIQ to avoid starvation situation caused by long time full access of GPU by other VFs. Signed-off-by:
Jiawei Gu <Jiawei.Gu@amd.com> Reviewed-by:
Emily.Deng <Emily.Deng@amd.com> Signed-off-by:
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Aric Cyr authored
This version brings along following fixes: - Fix error handling in dc/dcn10/dcn10_hw_sequencer_debug.c - DIO Supported for virtual displays - memset dmub_rb_cmd to 0 which fixes issues talking with firmware - fix 64bit division issue on 32bit OS - move edp sink present detection to hw init to fix hang - reverts a patch that caused 3x4K60 displays over MST with DSC enabled to not light up Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Acked-by:
Anson Jacob <Anson.Jacob@amd.com> Signed-off-by:
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Anthony Koo authored
Add new definition and union for dmub_rb_cmd_dig1_transmitter_control Signed-off-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
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Dale Zhao authored
It is possible for ret_vsnprintf to be assigned negative value in error cases. As an unsigned variable, negative values which are stored in their 2's complement form gets treated as a positive number. This will led to treating bad cases as good ones. eg: -1 gets stored as 0xFFFFFFFF on a 32 bit system Signed-off-by:
Dale Zhao <dale.zhao@amd.com> Reviewed-by:
Yongqiang Sun <yongqiang.sun@amd.com> Acked-by:
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Wesley Chalmers authored
[WHY] Virtual displays do not use the backend of the pipe, and so have infinite backend bandwidth. [HOW] Add a skip_dio_check bool to the VBA struct, which is used to override the DIOSupport calculations. Signed-off-by:
Wesley Chalmers <Wesley.Chalmers@amd.com> Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
Chris Park <Chris.Park@amd.com> Signed-off-by:
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Wyatt Wood authored
[Why] Since dmub_rb_cmds are not initialized to 0, the header is filled with invalid data. This is causing issues on the fw side. [How] Initialize dmub_rb_cmd unions to 0. Signed-off-by:
Wyatt Wood <wyatt.wood@amd.com> Reviewed-by:
Josip Pavic <Josip.Pavic@amd.com> Acked-by:
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Lang Yu authored
Replace "/" with div_u64 for 64bit division on 32bit OS. Signed-off-by:
Lang Yu <Lang.Yu@amd.com> Reviewed-by:
Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by:
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Eric Yang authored
[Why] At SW init, we may not be ready to do detect eDP sink. Signed-off-by:
Eric Yang <Eric.Yang2@amd.com> Reviewed-by:
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Jun Lei authored
3x4K60 displays over MST with DSC enabled was not able to light up due to this patch. Signed-off-by:
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Qingqing Zhuo authored
[Why] Current implementation of mod_hdcp_hdcp2_validate_ake_cert() does not process HDCP status message TA_HDCP2_MSG_AUTHENTICATION_STATUS__SIGNATURE_CERTIFICAT_ERROR. As a result, when there is a signature certificate error, mod_hdcp_hdcp2_validate_ake_cert would return the default status, which is success. [How] For all messages other than TA_HDCP2_MSG_AUTHENTICATION_STATUS__SUCCESS and TA_HDCP2_MSG_AUTHENTICATION_STATUS__RECEIVERID_REVOKED, return status as failure. Signed-off-by:
Qingqing Zhuo <qingqing.zhuo@amd.com> Reviewed-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Acked-by:
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Derek Lai authored
[Why and How] VBIOS program DIG_CLK_PATTERN using engine ID instead of PHY ID. Workaround by writing value for 0x1f (for HDMI) after calling vbios. Signed-off-by:
Derek Lai <Derek.Lai@amd.com> Reviewed-by:
Tony Cheng <Tony.Cheng@amd.com> Acked-by:
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Fangzhi Zuo authored
Signed-off-by:
Fangzhi Zuo <Jerry.Zuo@amd.com> Reviewed-by:
Mikita Lipski <Mikita.Lipski@amd.com> Acked-by:
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Tao Zhou authored
As dimgrey_cavefish driver is stable enough, set gpu recovery as default in HW hang for dimgrey_cavefish. Signed-off-by:
Tao Zhou <tao.zhou1@amd.com> Reviewed-by:
Jiansong Chen <Jiansong.Chen@amd.com> Signed-off-by:
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Kenneth Feng authored
Enable LCLK deep sleep and it works if we enable ASPM: modprobe amdgpu aspm=1 Signed-off-by:
Kenneth Feng <kenneth.feng@amd.com> Reviewed-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
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Alex Deucher authored
If device suspend fails when we attempt to runtime suspend, reset the runpm flag. Acked-by:
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Alex Deucher authored
the flag used by kfd is not actually related to fbcon, it just happens to align. Use the runpm flag instead so that we can decouple it from the fbcon flag. v2: fix resume as well Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by:
Rajneesh Bhardwaj <rajneesh.bhardwaj@amd.com> Acked-by:
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Alex Deucher authored
These are already called in amdgpu_device_suspend/resume which are already called in the same functions. Acked-by:
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Alex Deucher authored
Use generic PCI reset for GPU reset if the user specifies PCI reset as the reset mechanism. This should in general only be used for validation. Acked-by:
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Alex Deucher authored
Use generic PCI reset for GPU reset if the user specifies PCI reset as the reset mechanism. This should in general only be used for validation. Acked-by:
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Alex Deucher authored
Use generic PCI reset for GPU reset if the user specifies PCI reset as the reset mechanism. This should in general only be used for validation. Acked-by:
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Alex Deucher authored
This allows us to use generic PCI reset mechanisms (FLR, SBR) as a reset mechanism to verify that the generic PCI reset mechanisms are working properly. Acked-by:
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Alex Deucher authored
Drop duplicate reset method logging, whitespace changes. Acked-by:
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Alex Deucher authored
Drop duplicate reset method logging, whitespace changes. Acked-by:
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Alex Deucher authored
Drop duplicate reset method logging, whitespace changes. Acked-by:
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Xiaomeng Hou authored
Implement hwmon API for reading/setting slow and fast PPT limit. APU power is managed to system-level requirements through the PPT (package power tracking) feature. PPT is intended to limit power to the requirements of the power source and could be dynamically updated to maximize APU performance within the system power budget. Here FAST_PPT_LIMIT manages the ~10 ms moving average of APU power, while SLOW_PPT_LIMIT manages the configurable, thermally significant moving average of APU power (default ~5000 ms). User could read slow/fast ppt limit using command "cat power*_cap" or "sensors" in the hwmon device directory. User could adjust values of slow/fast ppt limit as needed depending on workloads through command "echo ## > power*_cap". Example: $ echo 15000000 > power1_cap $ echo 18000000 > power2_cap $ sensors amdgpu-pci-0300 Adapter: PCI adapter slowPPT: 9.04W (cap = 15.00 W) fastPPT: 9.04W (cap = 18.00 W) v2: align with existing interfaces for the getting/setting of PPT limits. Encode the upper 8 bits of limit value to distinguish slow and fast power limit type. Signed-off-by:Xiaomeng Hou <Xiaomeng.Hou@amd.com> Reviewed-by:
Lijo Lazar <lijo.lazar@amd.com> Signed-off-by:
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Xiaomeng Hou authored
The original smu_get_power_limit callback accepts the power limit level parameter as bool which limits to max and current. For possible needs to retrieve other level like min, extend the parameter type using enum. Signed-off-by:
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Xiaomeng Hou authored
Add PP messages for reading/setting Fast PPT and Slow PPT limit. Signed-off-by:
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Nirmoy Das authored
To achieve the best QoS for high priority compute jobs it is required to limit waves on other compute pipes as well. This patch will set min value in non high priority mmSPI_WCL_PIPE_PERCENT_CS[0-3] registers to minimize the impact of normal/low priority compute jobs over high priority compute jobs. Signed-off-by:
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Wayne Lin authored
[Why & How] On DCN1.0, need otg vertical line interrupt to get appropriate timing to achieve specific feature request. Add otg vertical interrupt0 support for registers which operation is vertical sensitive. Signed-off-by:
Wayne Lin <Wayne.Lin@amd.com> Acked-by:
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Wayne Lin authored
[Why & How] In order to get appropriate timing for registers which read/write is vertical line sensitive, add new IRQ source variable. This interrupt is triggered by specific vertical line, Signed-off-by:
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Kevin Wang authored
simplify the list operation. Signed-off-by:
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Kevin Wang authored
the soft gpu metrics is not asic related data structure. unify them to reduce duplicate code. Signed-off-by:
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