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  1. 20 Sep, 2023 3 commits
  3. 24 May, 2023 1 commit
  5. 16 May, 2023 1 commit
  7. 15 May, 2023 2 commits
  9. 13 Apr, 2023 1 commit
  11. 12 Apr, 2023 1 commit
  13. 21 Mar, 2023 1 commit
  15. 20 Mar, 2023 1 commit
    • Ville Syrjälä's avatar
      drm/i915: Update vblank timestamping stuff on seamless M/N change · 59ad01c7
      Ville Syrjälä authored 
      When we change the M/N values seamlessly during a fastset we should
also update the vblank timestamping stuff to make sure the vblank
timestamp corrections/guesstimations come out exact.

Note that only crtc_clock and framedur_ns can actually end up
changing here during fastsets. Everything else we touch can
only change during full modesets.

Technically we should try to do this exactly at the start of
vblank, but that would require some kind of double buffering
scheme. Let's skip that for now and just update things right
after the commit has been submitted to the hardware. This
means the information will be properly up to date when the
vblank irq handler goes to work. Only if someone ends up
querying some vblanky stuff in between the commit and start
of vblank may we see a slight discrepancy.

Also this same problem really exists for the DRRS downclocking
stuff. But as that is supposed to be more or less transparent
to the user, and it only drops to low gear after a long delay
(1 sec currently) we probably don't have to worry about it.
Any time something is actively submitting updates DRRS will
remain in high gear and so the timestamping constants will
match the hardware state.
Reviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
Reviewed-by: default avatarMitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Fixes: e6f29923 ("drm/i915: Allow M/N change during fastset on bdw+")
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230310235828.17439-1-ville.syrjala@linux.intel.com
(cherry picked from commit 8cb1f95c)
Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
      59ad01c7
  17. 18 Mar, 2023 1 commit
    • Ville Syrjälä's avatar
      drm/i915: Update vblank timestamping stuff on seamless M/N change · 8cb1f95c
      Ville Syrjälä authored 
      When we change the M/N values seamlessly during a fastset we should
also update the vblank timestamping stuff to make sure the vblank
timestamp corrections/guesstimations come out exact.

Note that only crtc_clock and framedur_ns can actually end up
changing here during fastsets. Everything else we touch can
only change during full modesets.

Technically we should try to do this exactly at the start of
vblank, but that would require some kind of double buffering
scheme. Let's skip that for now and just update things right
after the commit has been submitted to the hardware. This
means the information will be properly up to date when the
vblank irq handler goes to work. Only if someone ends up
querying some vblanky stuff in between the commit and start
of vblank may we see a slight discrepancy.

Also this same problem really exists for the DRRS downclocking
stuff. But as that is supposed to be more or less transparent
to the user, and it only drops to low gear after a long delay
(1 sec currently) we probably don't have to worry about it.
Any time something is actively submitting updates DRRS will
remain in high gear and so the timestamping constants will
match the hardware state.
Reviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
Reviewed-by: default avatarMitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Fixes: e6f29923 ("drm/i915: Allow M/N change during fastset on bdw+")
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230310235828.17439-1-ville.syrjala@linux.intel.com
      8cb1f95c
  19. 23 Feb, 2023 1 commit
  21. 18 Jan, 2023 1 commit
  23. 22 Oct, 2022 2 commits
  25. 07 Oct, 2022 1 commit
  27. 30 Sep, 2022 1 commit
  29. 26 Jul, 2022 1 commit
  31. 08 Apr, 2022 1 commit
  33. 06 Apr, 2022 1 commit
  35. 14 Mar, 2022 1 commit
  37. 08 Mar, 2022 1 commit
  39. 03 Mar, 2022 1 commit
    • Ville Syrjälä's avatar
      drm/i915: Fix the async flip wm0/ddb optimization · 2e084371
      Ville Syrjälä authored 
      The current implementation of the async flip wm0/ddb optimization
does not work at all. The biggest problem is that we skip the
whole intel_pipe_update_{start,end}() dance and thus never actually
complete the commit that is trying to do the wm/ddb change.

To fix this we need to move the do_async_flip flag to the crtc
state since we handle commits per-pipe, not per-plane.

Also since all planes can now be included in the first/last
"async flip" (which gets converted to a sync flip to do the
wm/ddb mangling) we need to be more careful when checking if
the plane state is async flip comptatible. Only planes doing
the async flip should be checked and other planes are perfectly
fine not adhereing to any async flip related limitations.

However for subsequent commits which are actually going do the
async flip in hardware we want to make sure no other planes
are in the state. That should never happen assuming we did our
job correctly, so we'll toss in a WARN to make sure we catch
any bugs here.

Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Fixes: c3639f3b ("drm/i915: Use wm0 only during async flips for DG2")
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220214105532.13049-4-ville.syrjala@linux.intel.comReviewed-by: default avatarStanislav Lisovskiy <stanislav.lisovskiy@intel.com>
      2e084371
  41. 05 Jan, 2022 1 commit
  43. 09 Dec, 2021 4 commits
  45. 03 Dec, 2021 1 commit
  47. 23 Nov, 2021 1 commit
  49. 18 Nov, 2021 2 commits
  51. 09 Nov, 2021 2 commits
    • Ville Syrjälä's avatar
      drm/i915: Use vblank workers for gamma updates · 2bbc6fca
      Ville Syrjälä authored 
      The pipe gamma registers are single buffered so they should only
be updated during the vblank to avoid screen tearing. In fact they
really should only be updated between start of vblank and frame
start because that is the only time the pipe is guaranteed to be
empty. Already at frame start the pipe begins to fill up with
data for the next frame.

Unfortunately frame start happens ~1 scanline after the start
of vblank which in practice doesn't always leave us enough time to
finish the gamma update in time (gamma LUTs can be several KiB of
data we have to bash into the registers). However we must try our
best and so we'll add a vblank work for each pipe from where we
can do the gamma update. Additionally we could consider pushing
frame start forward to the max of ~4 scanlines after start of
vblank. But not sure that's exactly a validated configuration.
As it stands the ~100 first pixels tend to make it through with
the old gamma values.

Even though the vblank worker is running on a high prority thread
we still have to contend with C-states. If the CPU happens be in
a deep C-state when the vblank interrupt arrives even the irq
handler gets delayed massively (I've observed dozens of scanlines
worth of latency). To avoid that problem we'll use the qos mechanism
to keep the CPU awake while the vblank work is scheduled.

With all this hooked up we can finally enjoy near atomic gamma
updates. It even works across several pipes from the same atomic
commit which previously was a total fail because we did the
gamma updates for each pipe serially after waiting for all
pipes to have latched the double buffered registers.

In the future the DSB should take over this responsibility
which will hopefully avoid some of these issues.

Kudos to Lyude for finishing the actual vblank workers.
Works like the proverbial train toilet.

v2: Add missing intel_atomic_state fwd declaration
v3: Clean up properly when not scheduling the worker
v4: Clean up the rest and add tracepoints
v5: s/intel_wait_for_vblank_works/intel_wait_for_vblank_workers/ (Jani,Uma)

CC: Lyude Paul <lyude@redhat.com>
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211020223339.669-4-ville.syrjala@linux.intel.comReviewed-by: default avatarUma Shankar <uma.shankar@intel.com>
      2bbc6fca
    • Ville Syrjälä's avatar
      drm/i915: Do vrr push before sampling the frame counter · 6f9976bd
      Ville Syrjälä authored 
      Do the vrr push before we sample the frame counter to
know when the commit has been latched. Doing these in the
wrong order could lead us to complete the flip before it
has actually happened.

Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211020223339.669-3-ville.syrjala@linux.intel.comReviewed-by: default avatarUma Shankar <uma.shankar@intel.com>
      6f9976bd
  53. 30 Jul, 2021 1 commit
  55. 24 Jun, 2021 1 commit
  57. 14 Apr, 2021 1 commit
    • Lucas De Marchi's avatar
      drm/i915/display: rename display version macros · 93e7e61e
      Lucas De Marchi authored 
      While converting the rest of the driver to use GRAPHICS_VER() and
MEDIA_VER(), following what was done for display, some discussions went
back on what we did for display:

	1) Why is the == comparison special that deserves a separate
	macro instead of just getting the version and comparing directly
	like is done for >, >=, <=?

	2) IS_DISPLAY_RANGE() is weird in that it omits the "_VER" for
	brevity. If we remove the current users of IS_DISPLAY_VER(), we
	could actually repurpose it for a range check

With (1) there could be an advantage if we used gen_mask since multiple
conditionals be combined by the compiler in a single and instruction and
check the result. However a) INTEL_GEN() doesn't use the mask since it
would make the code bigger everywhere else and b) in the cases it made
sense, it also made sense to convert to the _RANGE() variant.

So here we repurpose IS_DISPLAY_VER() to work with a [ from, to ] range
like was the IS_DISPLAY_RANGE() and convert the current IS_DISPLAY_VER()
users to use == and != operators. Aside from the definition changes,
this was done by the following semantic patch:

	@@ expression dev_priv, E1; @@
	- !IS_DISPLAY_VER(dev_priv, E1)
	+ DISPLAY_VER(dev_priv) != E1

	@@ expression dev_priv, E1; @@
	- IS_DISPLAY_VER(dev_priv, E1)
	+ DISPLAY_VER(dev_priv) == E1

	@@ expression dev_priv, from, until; @@
	- IS_DISPLAY_RANGE(dev_priv, from, until)
	+ IS_DISPLAY_VER(dev_priv, from, until)

Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
Signed-off-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
[Jani: Minor conflict resolve while applying.]
Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20210413051002.92589-4-lucas.demarchi@intel.com
      93e7e61e
  59. 23 Mar, 2021 2 commits
    • Matt Roper's avatar
      drm/i915/display: Simplify GLK display version tests · 2b5a4562
      Matt Roper authored 
      GLK has always been a bit of a special case since it reports INTEL_GEN()
as 9, but has version 10 display IP.  Now we can properly represent the
display version as 10 and simplify the display generation tests
throughout the display code.

Aside from manually adding the version to the glk_info structure, the
rest of this patch is generated with a Coccinelle semantic patch.  Note
that we also need to switch any code that matches gen10 today but *not*
GLK to be CNL-specific:

        @@ expression dev_priv; @@
        - DISPLAY_VER(dev_priv) > 9
        + DISPLAY_VER(dev_priv) >= 10

        @@ expression dev_priv, E; @@
        (
        - DISPLAY_VER(dev_priv) >= 10 && E
        + (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv)) && E
        |
        - DISPLAY_VER(dev_priv) >= 10
        + DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv)
        |
        - IS_DISPLAY_RANGE(dev_priv, 10, E)
        + IS_DISPLAY_RANGE(dev_priv, 11, E) || IS_CANNONLAKE(dev_priv)
        )

        @@ expression dev_priv, E, E2; @@
        (
        - (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
        + IS_DISPLAY_VER(dev_priv, 10)
        |
        - E || IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)
        + E || IS_DISPLAY_VER(dev_priv, 10)
        |
        - (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv))
        + IS_DISPLAY_VER(dev_priv, 10)
        |
        - IS_GEMINILAKE(dev_priv) || E || IS_CANNONLAKE(dev_priv)
        + E || IS_DISPLAY_VER(dev_priv, 10)
        |
        - E || IS_GEMINILAKE(dev_priv) || E2 || IS_CANNONLAKE(dev_priv)
        + E || E2 || IS_DISPLAY_VER(dev_priv, 10)
        |
        - (IS_DISPLAY_VER(dev_priv, 10) || IS_GEMINILAKE(dev_priv))
        + IS_DISPLAY_VER(dev_priv, 10)
        |
        - (IS_GEMINILAKE(dev_priv) || IS_DISPLAY_VER(dev_priv, 10))
        + IS_DISPLAY_VER(dev_priv, 10)
        )

        @@ expression dev_priv; @@
        - (IS_DISPLAY_VER(dev_priv, 9) && !IS_GEMINILAKE(dev_priv))
        + IS_DISPLAY_VER(dev_priv, 9)

        @@ expression dev_priv; @@
        (
        - !(DISPLAY_VER(dev_priv) >= 11 || IS_DISPLAY_VER(dev_priv, 10))
        + DISPLAY_VER(dev_priv) < 10
        |
        - (DISPLAY_VER(dev_priv) >= 11 || IS_DISPLAY_VER(dev_priv, 10))
        + DISPLAY_VER(dev_priv) >= 10
        )

        @@ expression dev_priv, E; @@
        - E || DISPLAY_VER(dev_priv) >= 11 || IS_DISPLAY_VER(dev_priv, 10)
        + E || DISPLAY_VER(dev_priv) >= 10

        @@ expression dev_priv, E; @@
        - (IS_DISPLAY_RANGE(dev_priv, 11, E) || IS_DISPLAY_VER(dev_priv, 10))
        + IS_DISPLAY_RANGE(dev_priv, 10, E)

        @@ expression dev_priv; @@
        (
        - DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv) || IS_GEN9_LP(dev_priv)
        + DISPLAY_VER(dev_priv) >= 10 || IS_GEN9_LP(dev_priv)
        |
        - IS_GEN9_LP(dev_priv) || DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv)
        + IS_GEN9_LP(dev_priv) || DISPLAY_VER(dev_priv) >= 10
        )

        @@ expression dev_priv, E; @@
        - !(DISPLAY_VER(dev_priv) >= E)
        + DISPLAY_VER(dev_priv) < E

v2:
 - Convert gen10 conditions that don't include GLK into CNL conditions.
   (Ville)

v3:
 - Rework coccinelle rules so that "ver>=10" turns into "ver>=11||is_cnl." (Ville)

v3.1:
 - Manually re-add the ".display.version = 10" to glk_info after
   regenerating patch via Coccinelle.

v4:
 - Also apply cocci rules to intel_pm.c and i915_irq.c!  (CI)

Cc: Ville Syrjälä <ville.syrjala@intel.com>
Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210322233840.4056851-1-matthew.d.roper@intel.com
      2b5a4562
    • Matt Roper's avatar
      drm/i915/display: Eliminate most usage of INTEL_GEN() · 005e9537
      Matt Roper authored 
      Use Coccinelle to convert most of the usage of INTEL_GEN() and IS_GEN()
in the display code to use DISPLAY_VER() comparisons instead.  The
following semantic patch was used:

        @@ expression dev_priv, E; @@
        - INTEL_GEN(dev_priv) == E
        + IS_DISPLAY_VER(dev_priv, E)

        @@ expression dev_priv; @@
        - INTEL_GEN(dev_priv)
        + DISPLAY_VER(dev_priv)

        @@ expression dev_priv; expression E; @@
        - IS_GEN(dev_priv, E)
        + IS_DISPLAY_VER(dev_priv, E)

        @@
        expression dev_priv;
        expression from, until;
        @@
        - IS_GEN_RANGE(dev_priv, from, until)
        + IS_DISPLAY_RANGE(dev_priv, from, until)

There are still some display-related uses of INTEL_GEN() in intel_pm.c
(watermark code) and i915_irq.c.  Those will be updated separately.

v2:
 - Use new IS_DISPLAY_RANGE and IS_DISPLAY_VER helpers.  (Jani)
Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Reviewed-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210320044245.3920043-4-matthew.d.roper@intel.com
      005e9537
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