Add WM8904 based analog sound card to Dahlia carrier board.
Reviewed-by: Jai Luthra <j-luthra@ti.com>
Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Link: https://lore.kernel.org/r/20230807202159.13095-5-francesco@dolcini.itSigned-off-by: Nishanth Menon <nm@ti.com>

Add NAU8822 based analog sound card to Development carrier board.
Reviewed-by: Jai Luthra <j-luthra@ti.com>
Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Link: https://lore.kernel.org/r/20230807202159.13095-4-francesco@dolcini.itSigned-off-by: Nishanth Menon <nm@ti.com>

Set AUDIO_EXT_REFCLK1, used as I2S_1_MCLK on Verdin AM62 family, to 25MHz
(this is the only valid option according to TI [1]).

[1] https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1188051/am625-audio_ext_refclk1-clock-output---dts-support/4476322#4476322Reviewed-by: Jai Luthra <j-luthra@ti.com>
Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Link: https://lore.kernel.org/r/20230807202159.13095-3-francesco@dolcini.itSigned-off-by: Nishanth Menon <nm@ti.com>

On AM62-based SoCs the AUDIO_REFCLKx clocks can be used as an input to
external peripherals when configured through CTRL_MMR, so add the
clock nodes.
Signed-off-by: Jai Luthra <j-luthra@ti.com>
Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Link: https://lore.kernel.org/r/20230807202159.13095-2-francesco@dolcini.itSigned-off-by: Nishanth Menon <nm@ti.com>

Due to non-addressable regions in J721S2 SOC wkup_pmx was split
into four regions from wkup_pmx0 to wkup_pmx3.

Correcting OSPI1 pin mux, which now falls under wkup_pmx1.
Along with that removing unused pin mux for OSPI-0.

Fixes: 6bc829ce ("arm64: dts: ti: k3-j721s2: Fix wkup pinmux range")
Signed-off-by: Udit Kumar <u-kumar1@ti.com>
Reviewed-by: Vaishnav Achath <vaishnav.a@ti.com>
Link: https://lore.kernel.org/r/20230804075341.3858488-1-u-kumar1@ti.comSigned-off-by: Nishanth Menon <nm@ti.com>

After splitting wkup_pmx pin mux for J784S4 into four regions.
Pin mux offset for OSPI nodes were not updated to align with new
regions, due to this while setting ospi pin muxes out of range
error was seen.

Pin mux offsets for OSPI nodes are corrected in this patch.

Fixes: 14462bd0 ("arm64: dts: ti: k3-j784s4: Fix wakeup pinmux range and pinctrl node offsets")
Signed-off-by: Udit Kumar <u-kumar1@ti.com>
Tested-by: Vaishnav Achath <vaishnav.a@ti.com>
Link: https://lore.kernel.org/r/20230802114126.162445-1-u-kumar1@ti.comSigned-off-by: Nishanth Menon <nm@ti.com>

On AM62ax there are no hardware interrupts routed to A53 GIC
interrupt controller for MCU MCAN IPs, so MCU MCAN nodes were
omitted from MCU dtsi.

Timer polling was introduced in commits [1][2] enabling 3x MCAN
on AM62ax, so now add MCU MCAN nodes to the mcu dtsi for the Cortex A53.

[1] commit b382380c ("can: m_can: Add hrtimer to generate software interrupt")
[2] commit bb410c03 ("dt-bindings: net: can: Remove interrupt properties for MCAN")
Signed-off-by: Judith Mendez <jm@ti.com>
Link: https://lore.kernel.org/r/20230804220137.425442-1-jm@ti.comSigned-off-by: Nishanth Menon <nm@ti.com>

AM68-SK has an HDMI port. The bridge used is TI-TFP410.
Add support to enable the connection:
DSS => TI TFP410 DPI-to-DVI Bridge => HDMI connector
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
Reviewed-by: Aradhya Bhatia <a-bhatia1@ti.com>
Link: https://lore.kernel.org/r/20230803081800.368582-3-j-choudhary@ti.comSigned-off-by: Nishanth Menon <nm@ti.com>

Add DSS node for J721S2 SoC. DSS IP in J721S2 is
same as DSS IP in J721E, so same compatible is used.
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
Reviewed-by: Aradhya Bhatia <a-bhatia1@ti.com>
Link: https://lore.kernel.org/r/20230803081800.368582-2-j-choudhary@ti.comSigned-off-by: Nishanth Menon <nm@ti.com>

The name "clock" is not allowed for nodes, use "clock-controller" to
remove the DTS check warning.
Signed-off-by: Andrew Davis <afd@ti.com>
Link: https://lore.kernel.org/r/20230802174521.236255-3-afd@ti.comSigned-off-by: Nishanth Menon <nm@ti.com>

There are two nodes representing the same register space, this looks to
have been created by some merge or copy/paste error. Remove the second
instance of this node and move its children into the first instance.
Signed-off-by: Andrew Davis <afd@ti.com>
Link: https://lore.kernel.org/r/20230802174521.236255-2-afd@ti.comSigned-off-by: Nishanth Menon <nm@ti.com>

The other instances have been fixed, but AM62a seems to have been missed,
fix this here.
Signed-off-by: Andrew Davis <afd@ti.com>
Link: https://lore.kernel.org/r/20230802174521.236255-1-afd@ti.comSigned-off-by: Nishanth Menon <nm@ti.com>

USB0 is interfaced with a Type-C DRP connector and is managed via a
USB PD controller. Add support for the Type-C port with dual data
and power sink role.
Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20230725103651.1612-1-r-gunasekaran@ti.comSigned-off-by: Nishanth Menon <nm@ti.com>

Add Verdin CAN_2 (TI AM62 MCU_MCAN0) and enable it on the Yavia,
Dahlia and Verdin Development board.
Signed-off-by: Hiago De Franco <hiago.franco@toradex.com>
Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Link: https://lore.kernel.org/r/20230802073635.11290-3-francesco@dolcini.itSigned-off-by: Nishanth Menon <nm@ti.com>

On AM62x there are no hardware interrupts routed to A53 GIC
interrupt controller for MCU MCAN IPs, so MCU MCAN nodes were
omitted from MCU dtsi.

Timer polling was introduced in commits [1][2] so now add MCU MCAN nodes
to the MCU dtsi for the Cortex A53.

[1] commit b382380c ("can: m_can: Add hrtimer to generate software interrupt")
[2] commit bb410c03 ("dt-bindings: net: can: Remove interrupt properties for MCAN")

[fd: fixed labels to match datasheet numbering, revised commit message,
     fixed reg/reg-names order]
Signed-off-by: Judith Mendez <jm@ti.com>
Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Link: https://lore.kernel.org/r/20230802073635.11290-2-francesco@dolcini.itSigned-off-by: Nishanth Menon <nm@ti.com>

Fix up outstanding pingroup node names to be compliant with the
upcoming pinctrl-single schema.
Reviewed-by: Tony Lindgren <tony@atomide.com>
Link: https://lore.kernel.org/r/20230802040347.2264339-1-nm@ti.comSigned-off-by: Nishanth Menon <nm@ti.com>

As the SD-card and WLAN are connected to the same SDHC interface (with a
GPIO-controlled mux), they are mutually exclusive. Provide Device Tree
overlays for both configurations.
Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com>
Link: https://lore.kernel.org/r/8ff8a6f1fdbe6ebb478f88bb0737628054c43c5b.1690463382.git.matthias.schiffer@ew.tq-group.comSigned-off-by: Nishanth Menon <nm@ti.com>

The TQMa64XxL is an LGA SoM based on the TI AM64x SoC family. Add DTS(I)
for the AM642 (2x Cortex-A53) variant and its combination with our
MBaX4XxL carrier board.
Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com>
Link: https://lore.kernel.org/r/2a635428c73b5ab0fe793e558db6b5d88edccf8c.1690463382.git.matthias.schiffer@ew.tq-group.comSigned-off-by: Nishanth Menon <nm@ti.com>

For now only the MBaX4Xx carrier board is defined.
Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/e4283d6af59c77d2f690e070eb948dd9142a2276.1690463382.git.matthias.schiffer@ew.tq-group.comSigned-off-by: Nishanth Menon <nm@ti.com>

The MAIN CPSW2G instance of CPSW on J721S2 SoC can be enabled with the GESI
Expansion Board connected to the J7 Common-Proc-Board. Use the overlay
to enable this.

Add alias for the MAIN CPSW2G port to enable kernel to fetch MAC address
directly from U-Boot.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Reviewed-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
Link: https://lore.kernel.org/r/20230726065407.378455-3-s-vadapalli@ti.comSigned-off-by: Nishanth Menon <nm@ti.com>

TI's J721S2 SoC has a MAIN CPSW2G instance of the CPSW Ethernet Switch.
Add devicetree node for it.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Reviewed-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
Link: https://lore.kernel.org/r/20230726065407.378455-2-s-vadapalli@ti.comSigned-off-by: Nishanth Menon <nm@ti.com>

The J7 GESI EXP board for J721E Common-Proc-Board supports RGMII mode.
Use the overlay to configure CPSW9G ports in RGMII-RXID mode.

Add aliases for CPSW9G ports to enable kernel to fetch MAC addresses
directly from U-Boot.
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Reviewed-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
Link: https://lore.kernel.org/r/20230725073057.96705-1-s-vadapalli@ti.comSigned-off-by: Nishanth Menon <nm@ti.com>

J784S4 EVM board has 32GB Non-Volatile UFS Memory.
So enabling UFS at board level.

UFS flash details are documented in board data sheet[1]
Section 1.2 Key Features and Interfaces.

[1] https://www.ti.com/lit/pdf/spruj62

Cc: Chai Wenle <Wenle.Chai@windriver.com>
Tested-by: Chai Wenle <Wenle.Chai@windriver.com>
Signed-off-by: Udit Kumar <u-kumar1@ti.com>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
Link: https://lore.kernel.org/r/20230725133607.2021379-3-u-kumar1@ti.comSigned-off-by: Nishanth Menon <nm@ti.com>

Add UFS support present in J784S4 SOC.

UFS is documented in J784S4 TRM[1]
Section 12.3.7 'Universal Flash Storage (UFS) Interface'

[1] http://www.ti.com/lit/zip/spruj52

Cc: Chai Wenle <Wenle.Chai@windriver.com>
Tested-by: Chai Wenle <Wenle.Chai@windriver.com>
Signed-off-by: Udit Kumar <u-kumar1@ti.com>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
Link: https://lore.kernel.org/r/20230725133607.2021379-2-u-kumar1@ti.comSigned-off-by: Nishanth Menon <nm@ti.com>

Add dts nodes for 6 EHRPWM instances on SoC. Disable EHRPWM nodes in the
dtsi files and only enable the ones that are actually pinned out on a
given board in the board dts file.
Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
Link: https://lore.kernel.org/r/20230721082150.12599-1-sinthu.raja@ti.comSigned-off-by: Nishanth Menon <nm@ti.com>

CAN instances 3 and 5 in the main domain are brought on the common
processor board through header J27 and J28. The CAN High and Low lines
from the SoC are routed through a mux on the SoM. The select lines need
to be set for the CAN signals to get connected to the transceivers on
the common processor board. Threfore, add respective mux, transceiver
dt nodes to add support for these CAN instances.
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
Signed-off-by: Bhavya Kapoor <b-kapoor@ti.com>
Link: https://lore.kernel.org/r/20230725085939.536766-1-b-kapoor@ti.comSigned-off-by: Nishanth Menon <nm@ti.com>

Introduce the debounce select mux macros to allow folks to setup
debounce configuration for pins. Each configuration selected maps
to a specific timing register as documented in appropriate Technical
Reference Manual (example:[1]).

[1] AM625x TRM (section 6.1.2.2): https://www.ti.com/lit/pdf/spruiv7Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
Link: https://lore.kernel.org/r/20230619131620.3286650-1-nm@ti.comSigned-off-by: Nishanth Menon <nm@ti.com>

Only SYSFW has control of SA3UL power.
From SYSFW 08.04.00.002, for security reasons, device ID for power
management of SA3UL has been removed.

"power-domains" property in crypto node tries to access
the SA3UL, for which it gets NACK and hence, SA3UL driver doesn't
probe properly.

Fixes: 8af89365 ("arm64: dts: ti: k3-am62-main: Enable crypto accelerator")
Signed-off-by: Kamlesh Gurudasani <kamlesh@ti.com>
Link: https://lore.kernel.org/r/20230614-sa3ul-v5-2-29dd2366fba3@ti.comSigned-off-by: Nishanth Menon <nm@ti.com>

Devices specific to compatible ti,am62-sa3ul don't have control over
power of SA3UL from main domain.

"power-domains" property in crypto node tries to access
the SA3UL power, for which it gets NACK and hence, driver doesn't
probe properly for those particular devices.

Make "power-domains" property as false for devices with
compatible ti,am62-sa3ul.

Fixes: 2ce9a729 ("dt-bindings: crypto: Add TI SA2UL crypto accelerator documentation")
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Kamlesh Gurudasani <kamlesh@ti.com>
Link: https://lore.kernel.org/r/20230614-sa3ul-v5-1-29dd2366fba3@ti.comSigned-off-by: Nishanth Menon <nm@ti.com>

The constants to define the idle state of SERDES MUX were defined in
bindings header. They are used only in DTS and driver uses the dt property
to set the idle state making it unsuitable for bindings.
The constants are moved to header next to DTS ("arch/arm64/boot/dts/ti/")
and all the references to bindings header are removed.
So add a warning to mark this bindings header as deprecated.
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Roger Quadros <rogerq@kernel.org>
Acked-by: Peter Rosin <peda@axentia.se>
Link: https://lore.kernel.org/r/20230721125732.122421-3-j-choudhary@ti.comSigned-off-by: Nishanth Menon <nm@ti.com>

The DTS uses constants for SERDES MUX idle state values which were earlier
provided as bindings header. But they are unsuitable for bindings.
So move these constants in a header next to DTS.

Also add J784S4 SERDES4 lane definitions which were missed earlier.
Suggested-by: Nishanth Menon <nm@ti.com>
Suggested-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Suggested-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/linux-arm-kernel/b24c2124-fe3b-246c-9af9-3ecee9fb32d4@kernel.org/Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Roger Quadros <rogerq@kernel.org>
Acked-by: Peter Rosin <peda@axentia.se>
Link: https://lore.kernel.org/r/20230721125732.122421-2-j-choudhary@ti.comSigned-off-by: Nishanth Menon <nm@ti.com>

wkup_i2c0 and associated eeprom device node were duplicated,
This patch fixes the node duplication.

Fixes: 4af03328 ("arm64: dts: ti: k3-j721e-som-p0: Enable wakeup_i2c0 and eeprom")
Signed-off-by: Udit Kumar <u-kumar1@ti.com>
Link: https://lore.kernel.org/r/20230721082344.1534094-1-u-kumar1@ti.comSigned-off-by: Nishanth Menon <nm@ti.com>

TI EHRPWM compatible is just ti,*-ehrpwm-tbclk without needing a
syscon compatibility.

Fixes the following dtbs_check warnings:
 compatible: [''ti,am654-ehrpwm-tbclk, 'syscon'] is too long
 compatible: ['ti,am64-epwm-tbclk', 'syscon'] is too long
 compatible: ['ti,am62-epwm-tbclk', 'syscon'] is too long
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
Link: https://lore.kernel.org/r/20230713184759.3336536-1-nm@ti.comSigned-off-by: Nishanth Menon <nm@ti.com>

Add missing whitespace between node name/label and opening {.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: David Lechner <david@lechnology.com>
Link: https://lore.kernel.org/r/20230705145755.292927-2-krzysztof.kozlowski@linaro.orgSigned-off-by: Nishanth Menon <nm@ti.com>

The DTS code coding style expects exactly one space before and after '='
sign.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20230702185221.44319-1-krzysztof.kozlowski@linaro.orgSigned-off-by: Nishanth Menon <nm@ti.com>

We just sorted the entries and fields last release, so just out of a
perverse sense of curiosity, I decided to see if we can keep things
ordered for even just one release.

The answer is "No. No we cannot".

I suggest that all kernel developers will need weekly training sessions,
involving a lot of Big Bird and Sesame Street.  And at the yearly
maintainer summit, we will all sing the alphabet song together.

I doubt I will keep doing this.  At some point "perverse sense of
curiosity" turns into just a cold dark place filled with sadness and
despair.

Repeats: 80e62bc8 ("MAINTAINERS: re-sort all entries and fields")
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>

Pull dma-mapping fixes from Christoph Hellwig:

 - swiotlb area sizing fixes (Petr Tesarik)

* tag 'dma-mapping-6.5-2023-07-09' of git://git.infradead.org/users/hch/dma-mapping:
  swiotlb: reduce the number of areas to match actual memory pool size
  swiotlb: always set the number of areas before allocating the pool

Pull irq update from Borislav Petkov:

 - Optimize IRQ domain's name assignment

* tag 'irq_urgent_for_v6.5_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  irqdomain: Use return value of strreplace()

Pull x86 fpu fix from Borislav Petkov:

 - Do FPU AP initialization on Xen PV too which got missed by the recent
   boot reordering work

* tag 'x86_urgent_for_v6.5_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86/xen: Fix secondary processors' FPU initialization