- 18 Aug, 2016 1 commit
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Stephen Boyd authored
Now that we have clk_hw based provider APIs to register clks, we can get rid of struct clk pointers while registering clks in these drivers, allowing us to move closer to a clear split of consumer and provider clk APIs. We also remove some __init markings in header files as they're useless and we're in the area. Tested-by:
Jisheng Zhang <jszhang@marvell.com> Cc: Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by:
Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by:
Stephen Boyd <stephen.boyd@linaro.org> Signed-off-by:
Stephen Boyd <sboyd@codeaurora.org>
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- 17 Aug, 2016 1 commit
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Markus Elfring authored
The field "owner" is set by the core. Thus delete an unneeded initialisation. Generated by: scripts/coccinelle/api/platform_no_drv_owner.cocci Signed-off-by:
Markus Elfring <elfring@users.sourceforge.net> Signed-off-by:
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- 15 Aug, 2016 24 commits
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Stephen Boyd authored
We've started getting out of order, fix it. Signed-off-by: -
Stephen Boyd authored
* clk-qcom-9615: dt-bindings: clock: Update bindings for MDM9615 GCC and LCC clk: mdm9615: Add support for MDM9615 Clock Controllers dt-bindings: Add MDM9615 DT bindings include files for GCC and LCC
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Neil Armstrong authored
Acked-by:
Rob Herring <robh@kernel.org> Signed-off-by:
Neil Armstrong <narmstrong@baylibre.com> Signed-off-by:
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Neil Armstrong authored
In order to support the Qualcomm MDM9615 SoC, add support for the Global and LPASS Clock Controllers. Signed-off-by:
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Neil Armstrong authored
Signed-off-by:
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Stephen Boyd authored
* clk-meson-gxbb: clk: gxbb: add MMC gate clocks, and expose for DT
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Kevin Hilman authored
Add the SD/eMMC gate clocks and expose them for use by DT. While at it, also explose FCLK_DIV2 since this is one of the input clocks to the mux internal to each of the SD/eMMC blocks. Signed-off-by:
Kevin Hilman <khilman@baylibre.com> Tested-by:
Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by:
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Laxman Dewangan authored
Maxim Max77620 has one 32KHz clock output and the clock HW IP used on this PMIC is same as what it is there in the MAX77686. Add clock driver support for MAX77620 on the MAX77686 driver. CC: Krzysztof Kozlowski <k.kozlowski@samsung.com> CC: Javier Martinez Canillas <javier@dowhile0.org> Signed-off-by:
Laxman Dewangan <ldewangan@nvidia.com> Tested-by:
Krzysztof Kozlowski <k.kozlowski@samsung.com> Reviewed-by:
Javier Martinez Canillas <javier@osg.samsung.com> Signed-off-by:
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Laxman Dewangan authored
Maxim has used the same clock IP on multiple PMICs like MAX77686, MAX77802, MAX77620. Only differences are the number of clocks from these PMICs like MAX77686 has 3 clocks output, MAX776802 have two clock output and MAX77620 has one clock output. Add clock binding details and DT example for the MAX77620. Signed-off-by:
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Laxman Dewangan authored
The clock IP used on the Maxim PMICs max77686 and max77802 are same. The configuration of clock register is also same except the number of clocks. Define the common DT binding file for the clocks of Maxim PMICs MAX77686 and MAX77802. For this, remove the separate DT binding document file for maxim,max77802 and move all information to maxim,max77686 DT binding document. Signed-off-by:
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Laxman Dewangan authored
The clock IP used on the Maxim PMICs max77686 and max77802 are same. The configuration of clock register is also same except the number of clocks. Part of common code utilisation, there is 3 files for these chips clock driver, one for common and two files for driver registration. Combine both drivers into single file and move common code into same common file reduces the 2 files and make max77686 and max77802 clock driver in single fine. This driver does not depends on the parent driver structure. The regmap handle is acquired through regmap APIs for the register access. This combination of driver helps on adding clock driver for different Maxim PMICs which has similar clock IP like MAX77620 and MAX20024. Signed-off-by:
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Stephen Boyd authored
This function is only called by builtin code, but we always exported it and had marked it as __init before commit e4eda8e0 (clk: remove exported function from __init section, 2013-01-06) removed that marking. Given that it isn't used by modules, lets unexport it and add back __init. Cc: Denis Efremov <yefremov.denis@gmail.com> Signed-off-by:
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Stephen Boyd authored
This function is marked __init, so it can't possibly need to be exported to modules. Remove the marking. Cc: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: -
Stephen Boyd authored
Before commit 0861e5b8 (clk: Add clk_hw OF clk providers, 2016-02-05) __of_clk_get_from_provider() would return an error pointer of the provider's choosing if there was a provider registered and EPROBE_DEFER otherwise. After that commit, it would return EPROBE_DEFER regardless of whether or not the provider returned an error. This is odd and can lead to behavior where clk consumers keep probe deferring when they should be seeing some other error. Let's restore the previous behavior where we only return EPROBE_DEFER when there isn't a provider in our of_clk_providers list. Otherwise, return the error from the last provider we find that matches the node. Reported-by:
Masahiro Yamada <yamada.masahiro@socionext.com> Fixes: 0861e5b8 ("clk: Add clk_hw OF clk providers") Signed-off-by:
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Wei Yongjun authored
Use the builtin_platform_driver() macro to make the code simpler. Signed-off-by:
Wei Yongjun <weiyj.lk@gmail.com> Signed-off-by:
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Gregory CLEMENT authored
These clocks are the ones which will be used as source for the peripherals of the Armada 3700 SoC. On this SoC there is two blocks of clocks: the North bridge one and the South bridge one. Most of them are gatable. Most of the time their rate are their parent rated divided by a ratio depending of two registers. Their parent can be choose between the TBG clocks for most of them. However, some of them can't choose their parent or directly depend of the xtal clocks. Other ones do not use exactly the same pattern to find the ratio between their parent rate and their rate. For these reason each clock is a composite clock and the operations they use are different depending of the clock. According to the datasheet it would be possible to select the parent clock and the ratio, however currently the driver does not support it. Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by:
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Gregory CLEMENT authored
This commit adds the DT binding documentation for the peripheral clocks used in the Marvell Armada 3700 SoCs. Signed-off-by:
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Gregory CLEMENT authored
These clocks are children of the xtal clock and each one can be selected as a source for the peripheral clocks. According to the datasheet it should be possible to modify their rate, but currently it is not supported. Signed-off-by:
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Gregory CLEMENT authored
This commit adds the DT binding documentation for the Time Base Generator clock used in the Marvell Armada 3700 SoCs. Signed-off-by:
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Gregory CLEMENT authored
This clock is the parent of all the Armada 3700 clocks. It is a fixed rate clock which depends on the gpio configuration read when resetting the SoC. Signed-off-by:
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Gregory CLEMENT authored
This commit adds the DT binding documentation for the the Xtal clock on Armada 3700 used in the Marvell Armada 3700 SoCs. Signed-off-by:
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Peter Ujfalusi authored
The driver is to provide the functional clock to OMAP4/5 McPDM. The clock is named as pdmclk in the documentations so change the function names, structure names and variables to align with this. At the same time rename the driver from "twl6040-clk" to "twl6040-pdmclk". This can be done w/o regression since the clock driver is not in use at the moment, the MFD core driver is not even registering the device for it. Signed-off-by:
Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by:
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Peter Ujfalusi authored
In order ot be able to use the pdmclk clock via DT it need to be registered as of_clk_provide. Since the twl6040 clock driver does not have it's own DT node, use the parent's node for registering. Signed-off-by:
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Peter Ujfalusi authored
Since the drover only supports prepare callbacks, the use of is_enabled is not correct, it should be handling is_prepared. Signed-off-by:
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- 13 Aug, 2016 11 commits
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Grzegorz Jaszczyk authored
Both SATA and second USB3.0 interface are supported in Armada-39x SoC family. Add necessary clk description, so both xhci and sata drivers can be correctly initialized. The binding documentation has also been updated accordingly. Signed-off-by:
Grzegorz Jaszczyk <jaz@semihalf.com> Acked-by:
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by:
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Masahiro Yamada authored
This code is clear enough, but the intention will be even clearer with this. Signed-off-by:
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Ricardo Ribalda Delgado authored
Adds support for fixed-rate clock providers which have not been enabled via of_clk_init(). This is required by Device trees overlays that introduce clocks providers. Signed-off-by:
Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com> [sboyd@codeaurora.org: Make new private function static, don't check clk for NULL when unregistering in driver remove] Signed-off-by:
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Ricardo Ribalda Delgado authored
Adds support for fixed-factor clock providers which have not been enabled via of_clk_init(). This is required by Device trees overlays that introduce clocks providers. Signed-off-by:
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Ricardo Ribalda Delgado authored
Some clock providers can be initialized via of_clk_init() and also via platform device probe. Avoid double initialization of them by setting the OF_POPULATED flag. Signed-off-by:
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Ricardo Ribalda Delgado authored
This driver initializes a clock provider via sun8i_a23_apb0_setup and then continues the initialization on sun8i_a23_apb0_clk_probe. Use the new macro to notify the clk subsystem about this behaviour. Signed-off-by:
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Ricardo Ribalda Delgado authored
This driver initializes a clock provider via sun4i_a10_mod0_setup and then continues the initialization on sun4i_a10_mod0_clk_probe. Use the new macro to notify the clk subsystem about this behaviour. Signed-off-by:
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Ricardo Ribalda Delgado authored
This driver initializes a clock provider via lpc18xx_creg_clk_init and then continues the initialization on lpc18xx_creg_clk_probe. Use the new macro to notify the clk subsystem about this behaviour. Signed-off-by:
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Ricardo Ribalda Delgado authored
This driver initializes a clock provider via of_artpec6_clkctrl_setup and then continues the initialization on artpec6_clkctrl_probe. Use the new macro to notify the clk subsystem about this behaviour. Signed-off-by:
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Ricardo Ribalda Delgado authored
This will be used by drivers that requires initialization at of_clk_init() time and also during platform device probing. Signed-off-by:
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Geert Uytterhoeven authored
clk-divider uses clk_readl()/clk_writel() everywhere, except in clk_divider_round_rate(), where plain readl() is used. Change this to clk_readl(), as it makes a difference on powerpc. Fixes: e6d5e7d9 ("clk-divider: Fix READ_ONLY when divider > 1") Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by:
James Hogan <james.hogan@imgtec.com> Signed-off-by:
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- 12 Aug, 2016 3 commits
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Fabio Estevam authored
Booting the kernel on a imx7s-warp leads to several warnings like these: [ 0.000000] ------------[ cut here ]------------ [ 0.000000] WARNING: CPU: 0 PID: 0 at kernel/locking/lockdep.c:3536 lock_release+0x2f8/0x330 [ 0.000000] releasing a pinned lock [ 0.000000] ------------[ cut here ]------------ [ 0.000000] WARNING: CPU: 0 PID: 0 at kernel/locking/lockdep.c:2722 trace_hardirqs_on_caller+0x1ac/0x1f4 [ 0.000000] DEBUG_LOCKS_WARN_ON(unlikely(early_boot_irqs_disabled)) [ 0.000000] ---[ end trace cb88537fdc8fa201 ]--- [ 0.000000] bad: scheduling from the idle thread! [ 0.000000] CPU: 0 PID: 0 Comm: swapper/0 Tainted: G W 4.7.0-rc7-next-20160715 #404 [ 0.000000] ------------[ cut here ]------------ [ 0.000000] WARNING: CPU: 0 PID: 0 at kernel/time/sched_clock.c:179 sched_clock_register+0x44/0x1f8 [ 0.000000] Modules linked in: [ 0.000591] ------------[ cut here ]------------ [ 0.000610] WARNING: CPU: 0 PID: 0 at kernel/time/sched_clock.c:179 sched_clock_register+0x44/0x1f8 [ 0.002084] ------------[ cut here ]------------ [ 0.002104] WARNING: CPU: 0 PID: 0 at init/main.c:576 start_kernel+0x258/0x3b0 [ 0.002114] Interrupts were enabled early This fix is along the same lines as 5e33ebff ("clk: imx7d: do not set parent of ethernet time/ref clocks") and the explanation from that commit is: "The reason for the warning is that setting the parent enables the ENET PLL since we are using CLK_OPS_PARENT_ENABLE. Enabling the ENET PLL can cause clk_pllv3_wait_lock to sleep. See also: commit fc8726a2 ("clk: core: support clocks which requires parents enable (part 2)")." imx7s-warp does not even use the FEC interface, so we should not really configure the parent of IMX7D_ENET_AXI_ROOT_SRC in the common MX7 clock driver code. The dts file should use the assigned-clocks/assigned-clock-parents method, so simply remove the configuration of IMX7D_ENET_AXI_ROOT_SRC parent. Signed-off-by:
Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by:
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Stephen Boyd authored
The common clk framework has a patchwork associated with it. Update the maintainers file to reflect this. Cc: Michael Turquette <mturquette@baylibre.com> Signed-off-by: -
Michael Turquette authored
It's always nice to see families reunited, and this is equally true when talking about parent clocks and their children. However, if the orphan clk had a positive prepare_count or enable_count, then we would not migrate those counts up the parent chain correctly. This has manifested with the recent critical clocks feature, which often enables clocks very early, before their parents have been registered. Fixed by replacing the call to clk_core_reparent with calls to __clk_set_parent_{before,after}. Cc: James Liao <jamesjj.liao@mediatek.com> Cc: Erin Lo <erin.lo@mediatek.com> Signed-off-by:Michael Turquette <mturquette@baylibre.com> [sboyd@codeaurora.org: Recalc accuracies and rates too] Signed-off-by:
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