- 12 Feb, 2021 5 commits
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David S. Miller authored
Vignesh Raghavendra says: ==================== net: ti: am65-cpsw-nuss: Add switchdev driver This series adds switchdev support for AM65 CPSW NUSS driver to support multi port CPSW present on J721e and AM64 SoCs. It adds devlink hook to switch b/w switch mode and multi mac mode. v2: Rebased on latest net-next Update patch 1/4 with rationale for using devlink ====================
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Vignesh Raghavendra authored
J721e, J7200 and AM64 have multi port switches which can work in multi mac mode and in switch mode. Add documentation explaining how to use different modes. Borrowed from: Documentation/networking/device_drivers/ethernet/ti/cpsw_switchdev.rst Signed-off-by:
Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by:
David S. Miller <davem@davemloft.net>
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Vignesh Raghavendra authored
J721e, J7200 and AM64 have multi port switches which can work in multi mac mode and in switch mode. Add support for configuring this HW in switch mode using devlink and switchdev notifiers. Support is similar to existing CPSW switchdev implementation of TI's 32 bit platform like AM33/AM43/AM57. To enable switch mode: devlink dev param set platform/8000000.ethernet name switch_mode value true cmode runtime All configuration is implemented via switchdev API and notifiers. Supported: - SWITCHDEV_ATTR_ID_PORT_PRE_BRIDGE_FLAGS - SWITCHDEV_ATTR_ID_PORT_BRIDGE_FLAGS - SWITCHDEV_ATTR_ID_PORT_STP_STATE - SWITCHDEV_OBJ_ID_PORT_VLAN - SWITCHDEV_OBJ_ID_PORT_MDB - SWITCHDEV_OBJ_ID_HOST_MDB Hence AM65 CPSW switchdev driver supports: - FDB offloading - MDB offloading - VLAN filtering and offloading - STP Signed-off-by: -
Vignesh Raghavendra authored
Register netdevice notifiers in order to receive notification when individual MAC ports are added to the HW bridge. Signed-off-by:
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Vignesh Raghavendra authored
AM65 NUSS ethernet switch on K3 devices can be configured to work either in independent mac mode where each port acts as independent network interface (multi mac) or switch mode. Add devlink hooks to provide a way to switch b/w these modes. Rationale to use devlink instead of defaulting to bridge mode is that SoC use cases require to support multiple independent MAC ports with no switching so that users can use software bridges with multi-mac configuration (e.g: to support LAG, HSR/PRP, etc). Also, switching between multi mac and switch mode requires significant Port and ALE reconfiguration, therefore is easier to be made as part of mode change devlink hooks. It also allows to keep user interface similar to what was implemented for the previous generation of TI CPSW IP (on AM33/AM43/AM57 SoCs). Signed-off-by:
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- 11 Feb, 2021 35 commits
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David S. Miller authored
Rafał Miłecki says: ==================== bcm4908_enet: post-review fixes V2 of my BCM4908 Ethernet patchset was applied to the net-next.git and it was later that is received some extra reviews. I'm sending patches that handle pointed out issues. David: earler I missed that V2 was applied and I sent V3 and V4 of my inital patchset. Sorry for that. I think it's the best to ignore V3 and V4 I sent and proceed with this fixes patchset instead. ==================== Signed-off-by: -
Rafał Miłecki authored
Use le32_to_cpu() for reading __le32 struct field filled by hw. Signed-off-by:
Rafał Miłecki <rafal@milecki.pl> Reviewed-by:
Florian Fainelli <f.fainelli@gmail.com> Signed-off-by:
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Rafał Miłecki authored
Use ETH_FCS_LEN instead of magic value and drop incorrect + 2 Signed-off-by:
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Rafał Miłecki authored
1. Fix "ensable" typo noticed by Andrew 2. Fix chipset name in the struct net_device_ops variable Suggested-by:
Andrew Lunn <andrew@lunn.ch> Signed-off-by:
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Rafał Miłecki authored
It seems preferred to let compiler optimize code if applicable. While at it drop unused enet_umac_maskset(). Suggested-by:
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Rafał Miłecki authored
dma_alloc_coherent takes care of zeroing allocated memory Suggested-by:
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Rafał Miłecki authored
compatible string was updated to match normal naming convention so update driver as well Signed-off-by:
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Rafał Miłecki authored
It should be /included/ by every Ethernet controller binding. It adds support for various generic properties. Suggested-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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Rafał Miłecki authored
Rob pointed out that a normal convention is "brcm,bcm4908-enet" so update whole binding to match it. Suggested-by:
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git://git.kernel.org/pub/scm/linux/kernDavid S. Miller authored
el/git/bluetooth/bluetooth-next Johan Hedberg says: ==================== pull request: bluetooth-next 2021-02-11 Here's the main bluetooth-next pull request for 5.12: - Add support for advertising monitor offliading using Microsoft vendor extensions - Add firmware download support for MediaTek MT7921U USB devices - Suspend-related fixes for Qualcomm devices - Add support for Intel GarfieldPeak controller - Various other smaller fixes & cleanups Please let me know if there are any issues pulling. Thanks. ==================== Signed-off-by: -
David S. Miller authored
Geetha sowjanya says: ==================== Add Marvell CN10K support The current admin function (AF) driver and the netdev driver supports OcteonTx2 silicon variants. The same OcteonTx2's Resource Virtualization Unit (RVU) is carried forward to the next-gen silicon ie OcteonTx3, with some changes and feature enhancements. This patch set adds support for OcteonTx3 (CN10K) silicon and gets the drivers to the same level as OcteonTx2. No new OcteonTx3 specific features are added. Changes cover below HW level differences - PCIe BAR address changes wrt shared mailbox memory region - Receive buffer freeing to HW - Transmit packet's descriptor submission to HW - Programmable HW interface identifiers (channels) - Increased MTU support - A Serdes MAC block (RPM) configuration v5-v6 Rebased on top of latest net-next branch. v4-v5 Fixed sparse warnings. v3-v4 Fixed compiler warnings. v2-v3 Reposting as a single thread. Rebased on top latest net-next branch. v1-v2 Fixed check-patch reported issues. ==================== Signed-off-by: -
Hariprasad Kelam authored
MAC on CN10K silicon support loopback for selftest or debug purposes. This patch does necessary configuration to loopback packets upon receiving request from LMAC mapped RVU PF's netdev via mailbox. Also MAC (CGX) on OcteonTx2 silicon variants and MAC (RPM) on OcteonTx3 CN10K are different and loopback needs to be configured differently. Upper layer interface between RVU AF and PF netdev is kept same. Based on silicon variant appropriate fn() pointer is called to config the MAC. Signed-off-by:
Hariprasad Kelam <hkelam@marvell.com> Signed-off-by:
Geetha sowjanya <gakula@marvell.com> Signed-off-by:
Sunil Goutham <sgoutham@marvell.com> Reported-by:
kernel test robot <lkp@intel.com> Signed-off-by:
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Hariprasad Kelam authored
RPM supports below list of counters as an extension to existing counters * class based flow control pause frames * vlan/jabber/fragmented packets * fcs/alignment/oversized error packets This patch adds support to display supported RPM counters via debugfs and define new mbox rpm_stats to read all support counters. Signed-off-by:
Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by:
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Rakesh Babu authored
Flow control configuration is different for CGX(Octeontx2) and RPM(CN10K) functional blocks. This patch adds the necessary changes for RPM to support 802.3 pause frames configuration on cn10k platforms. Signed-off-by:
Rakesh Babu <rsaladi2@marvell.com> Signed-off-by:
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Hariprasad Kelam authored
CN10K supports max MTU of 16K on LMAC links and 64k on LBK links and Octeontx2 silicon supports 9K mtu on both links. Get the same from nix_get_hw_info mbox message in netdev probe. This patch also calculates receive buffer size required based on the MTU set. Signed-off-by:
Subbaraya Sundeep <sbhatta@marvell.com> Signed-off-by:
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Hariprasad Kelam authored
OcteonTx3 CN10K silicon supports bigger MTU when compared to 9216 MTU supported by OcteonTx2 silicon variants. Lookback interface supports upto 64K and RPM LMAC interfaces support upto 16K. This patch does the necessary configuration and adds support for PF/VF drivers to retrieve max packet size supported via mbox This patch also configures tx link credit by considering supported fifo size and max packet length for Octeontx3 silicon. This patch also removes platform specific name from the driver name. Signed-off-by:
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Subbaraya Sundeep authored
NIX uses unique channel numbers to identify the packet sources/sinks like CGX,LBK and SDP. The channel numbers assigned to each block are hardwired in CN9xxx silicon. The fixed channel numbers in CN9xxx are: 0x0 | a << 8 | b - LBK(0..3)_CH(0..63) 0x0 | a << 8 - Reserved 0x700 | a - SDP_CH(0..255) 0x800 | a << 8 | b << 4 | c - CGX(0..7)_LMAC(0..3)_CH(0..15) All the channels in the above fixed enumerator(with maximum number of blocks) are not required since some chips have less number of blocks. For CN10K silicon the channel numbers need to be programmed by software in each block with the base channel number and range of channels. This patch calculates and assigns the channel numbers to efficiently distribute the channel number range(0-4095) among all the blocks. The assignment is made based on the actual number of blocks present and also contiguously leaving no holes. The channel numbers remaining after the math are used as new CPT replay channels present in CN10K. Also since channel numbers are not fixed the transmit channel link number needed by AF consumers is calculated by AF and sent along with nix_lf_alloc mailbox response. Signed-off-by:
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Hariprasad Kelam authored
OcteonTx2's next gen platform the CN10K has RPM MAC which has a different serdes when compared to CGX MAC. Though the underlying HW is different, the CSR interface has been designed largely inline with CGX MAC, with few exceptions though. So we are using the same CGX driver for RPM MAC as well and will have a different set of APIs for RPM where ever necessary. This patch adds initial support for CN10K's RPM MAC i.e. the driver registration, communication with firmware etc. For communication with firmware, RPM provides a different IRQ when compared to CGX. The CGX and RPM blocks support different features. Currently few features like ptp, flowcontrol and higig are not supported by RPM. This patch adds new mailbox message "CGX_FEATURES_GET" to get the list of features supported by underlying MAC. RPM has different implementations for RX/TX stats. Unlike CGX, bar offset of stat registers are different. This patch adds support to access the same and dump the values in debugfs. Signed-off-by:
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Geetha sowjanya authored
This patch adds support to use new LMTST lines for NPA batch free and burst SQE flush. Adds new dev_hw_ops structure to hold platform specific functions and create new files cn10k.c and cn10k.h. Signed-off-by:
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Geetha sowjanya authored
On CN10K platform transmit/receive buffer alloc and free from/to hardware had changed to support burst operation. Whereas pervious silicon's only support single buffer free at a time. To Support the same firmware allocates a DRAM region for each PF/VF for storing LMTLINES. These LMTLINES are used for NPA batch free and for flushing SQE to the hardware. PF/VF LMTST region is accessed via BAR4. PFs LMTST region is followed by its VFs mbox memory. The size of region varies from 2KB to 256KB based on number of LMTLINES configured. This patch adds support for - Mapping PF/VF LMTST region. - Reserves 0-71 (RX + TX + XDP) LMTST lines for NPA batch free operation. - Reserves 72-512 LMTST lines for NIX SQE flush. Signed-off-by:
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Geetha sowjanya authored
On CN10K platform NIX RQ and SQ context structure got changed. This patch uses new mbox message "NIX_CN10K_AQ_ENQ" for NIX context initialization on CN10K platform. This patch also updates the nix_rx_parse_s and nix_sqe_sg_s structures to add packet steering bit feilds. Signed-off-by:
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Geetha sowjanya authored
On CN10K platform NPA and NIX context structure bit fields had changed to support new features like bandwidth steering etc. This patch dumps approprate context for CN10K platform. Signed-off-by:
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Geetha sowjanya authored
NIX hardware context structure got changed to accommodate new features like bandwidth steering, L3/L4 outer/inner checksum enable/disable etc., on CN10K platform. This patch defines new mbox message NIX_CN10K_AQ_INST for new NIX context initialization. This patch also updates the NPA context structures to accommodate bit field changes made for CN10K platform. This patch also removes Big endian bit fields from existing structures as its support got deprecated in current and upcoming silicons. Signed-off-by:
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Subbaraya Sundeep authored
Firmware allocates memory regions for PFs and VFs in DRAM. The PFs memory region is used for AF-PF and PF-VF mailbox. This mbox facilitate communication between AF-PF and PF-VF. On CN10K platform: The DRAM region allocated to PF is enumerated as PF BAR4 memory. PF BAR4 contains AF-PF mbox region followed by its VFs mbox region. AF-PF mbox region base address is configured at RVU_AF_PFX_BAR4_ADDR PF-VF mailbox base address is configured at RVU_PF(x)_VF_MBOX_ADDR = RVU_AF_PF()_BAR4_ADDR+64KB. PF access its mbox region via BAR4, whereas VF accesses PF-VF DRAM mailboxes via BAR2 indirect access. On CN9XX platform: Mailbox region in DRAM is divided into two parts AF-PF mbox region and PF-VF mbox region i.e all PFs mbox region is contiguous similarly all VFs. The base address of the AF-PF mbox region is configured at RVU_AF_PF_BAR4_ADDR. AF-PF1 mbox address can be calculated as RVU_AF_PF_BAR4_ADDR * mbox size. The base address of PF-VF mbox region for each PF is configure at RVU_AF_PF(0..15)_VF_BAR4_ADDR.PF access its mbox region via BAR4 and its VF mbox regions from RVU_PF_VF_BAR4_ADDR register, whereas VF access its mbox region via BAR4. This patch changes mbox initialization to support both CN9XX and CN10K platform. The patch also adds new hw_cap flag to setting hw features like TSO etc and removes platform specific name from the PF/VF driver name to make it appropriate for all supported platforms This patch also removes platform specific name from the PF/VF driver name to make it appropriate for all supported platforms Signed-off-by:
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Subbaraya Sundeep authored
Firmware allocates memory regions for PFs and VFs in DRAM. The PFs memory region is used for AF-PF and PF-VF mailbox. This mbox facilitates communication between AF-PF and PF-VF. On CN10K platform: The DRAM region allocated to PF is enumerated as PF BAR4 memory. PF BAR4 contains AF-PF mbox region followed by its VFs mbox region. AF-PF mbox region base address is configured at RVU_AF_PFX_BAR4_ADDR PF-VF mailbox base address is configured at RVU_PF(x)_VF_MBOX_ADDR = RVU_AF_PF()_BAR4_ADDR+64KB. PF access its mbox region via BAR4, whereas VF accesses PF-VF DRAM mailboxes via BAR2 indirect access. On CN9XX platform: Mailbox region in DRAM is divided into two parts AF-PF mbox region and PF-VF mbox region i.e all PFs mbox region is contiguous similarly all VFs. The base address of the AF-PF mbox region is configured at RVU_AF_PF_BAR4_ADDR. AF-PF1 mbox address can be calculated as RVU_AF_PF_BAR4_ADDR * mbox size. The base address of PF-VF mbox region for each PF is configure at RVU_AF_PF(0..15)_VF_BAR4_ADDR.PF access its mbox region via BAR4 and its VF mbox regions from RVU_PF_VF_BAR4_ADDR register, whereas VF access its mbox region via BAR4. This patch changes mbox initialization to support both CN9XX and CN10K platform. This patch also adds CN10K PTP subsystem and device IDs to ptp driver id table. Signed-off-by:
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David S. Miller authored
Stefan Chulski says: ==================== net: mvpp2: Add TX Flow Control support Armada hardware has a pause generation mechanism in GOP (MAC). The GOP generate flow control frames based on an indication programmed in Ports Control 0 Register. There is a bit per port. However assertion of the PortX Pause bits in the ports control 0 register only sends a one time pause. To complement the function the GOP has a mechanism to periodically send pause control messages based on periodic counters. This mechanism ensures that the pause is effective as long as the Appropriate PortX Pause is asserted. Problem is that Packet Processor that actually can drop packets due to lack of resources not connected to the GOP flow control generation mechanism. To solve this issue Armada has firmware running on CM3 CPU dedicated for Flow Control support. Firmware monitors Packet Processor resources and asserts XON/XOFF by writing to Ports Control 0 Register. MSS shared SRAM memory used to communicate between CM3 firmware and PP2 driver. During init PP2 driver informs firmware about used BM pools, RXQs, congestion and depletion thresholds. The pause frames are generated whenever congestion or depletion in resources is detected. The back pressure is stopped when the resource reaches a sufficient level. So the congestion/depletion and sufficient level implement a hysteresis that reduces the XON/XOFF toggle frequency. Packet Processor v23 hardware introduces support for RX FIFO fill level monitor. Patch "add PPv23 version definition" to differ between v23 and v22 hardware. Patch "add TX FC firmware check" verifies that CM3 firmware supports Flow Control monitoring. v12 --> v13 - Remove bm_underrun_protect module_param v11 --> v12 - Improve warning message in "net: mvpp2: add TX FC firmware check" patch v10 --> v11 - Improve "net: mvpp2: add CM3 SRAM memory map" comment - Move condition check to 'net: mvpp2: always compare hw-version vs MVPP21' patch v9 --> v10 - Add CM3 SRAM description to PPv2 documentation v8 --> v9 - Replace generic pool allocation with devm_ioremap_resource v7 --> v8 - Reorder "always compare hw-version vs MVPP21" and "add PPv23 version definition" commits - Typo fixes - Remove condition fix from "add RXQ flow control configurations" v6 --> v7 - Reduce patch set from 18 to 15 patches - Documentation change combined into a single patch - RXQ and BM size change combined into a single patch - Ring size change check moved into "add RXQ flow control configurations" commit v5 --> v6 - No change v4 --> v5 - Add missed Signed-off - Fix warnings in patches 3 and 12 - Add revision requirement to warning message - Move mss_spinlock into RXQ flow control configurations patch - Improve FCA RXQ non occupied descriptor threshold commit message v3 --> v4 - Remove RFC tag v2 --> v3 - Remove inline functions - Add PPv2.3 description into marvell-pp2.txt - Improve mvpp2_interrupts_mask/unmask procedure - Improve FC enable/disable procedure - Add priv->sram_pool check - Remove gen_pool_destroy call - Reduce Flow Control timer to x100 faster v1 --> v2 - Add memory requirements information - Add EPROBE_DEFER if of_gen_pool_get return NULL - Move Flow control configuration to mvpp2_mac_link_up callback ==================== Signed-off-by: -
Stefan Chulski authored
Patch check that TX FC firmware is running in CM3. If not, global TX FC would be disabled. Signed-off-by:
Stefan Chulski <stefanc@marvell.com> Acked-by:
Marcin Wojtas <mw@semihalf.com> Signed-off-by:
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Stefan Chulski authored
This patch fix GMAC TX flow control autoneg. Flow control autoneg wrongly were disabled with enabled TX flow control. Signed-off-by:
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Stefan Chulski authored
New FIFO flow control feature was added in PPv23. PPv2 FIFO polled by HW and trigger pause frame if FIFO fill level is below threshold. FIFO HW flow control enabled with CM3 RXQ&BM flow control with ethtool. Current FIFO thresholds is: 9KB for port with maximum speed 10Gb/s port 4KB for port with maximum speed 5Gb/s port 2KB for port with maximum speed 1Gb/s port Signed-off-by:
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Stefan Chulski authored
The PP2v23 hardware supports a feature allowing to double the size of BPPI by decreasing number of pools from 16 to 8. Increasing of BPPI size protect BM drop from BPPI underrun. Underrun could occurred due to stress on DDR and as result slow buffer transition from BPPE to BPPI. New BPPI threshold recommended by spec is: BPPI low threshold - 640 buffers BPPI high threshold - 832 buffers Supported only in PPv23. Signed-off-by:
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Stefan Chulski authored
This patch add ethtool flow control configuration support. Tx flow control retrieved correctly by ethtool get function. FW per port ethtool configuration capability added. Patch also takes care about mtu change procedure, if PPv2 switch BM pools during mtu change. Signed-off-by:
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Stefan Chulski authored
This patch adds RXQ flow control configurations. Flow control disabled by default. Minimum ring size limited to 1024 descriptors. Signed-off-by:
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Stefan Chulski authored
This patch enables global flow control in FW and in the phylink validate mask. Signed-off-by:
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Stefan Chulski authored
The firmware needs to monitor the RX Non-occupied descriptor bits for flow control to move to XOFF mode. These bits need to be unmasked to be functional, but they will not raise interrupts as we leave the RX exception summary bit in MVPP2_ISR_RX_TX_MASK_REG clear. Signed-off-by:
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Stefan Chulski authored
Flow Control periodic timer would be used if port in XOFF to transmit periodic XOFF frames. Signed-off-by:
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