- 27 Aug, 2013 10 commits
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Michael Ellerman authored
The symbols that name some of our exception trampolines are ahead of the location they name. In most cases this is OK because the code is tightly packed, but in some cases it means the symbol floats ahead of the correct location, eg: c000000000000ea0 <performance_monitor_pSeries_1>: ... c000000000000f00: 7d b2 43 a6 mtsprg 2,r13 Fix them all by moving the symbol after the set of the location. While we're moving them anyway, rename them to loose the camelcase and to make it clear that they are trampolines. Signed-off-by:Michael Ellerman <michael@ellerman.id.au> Signed-off-by:
Benjamin Herrenschmidt <benh@kernel.crashing.org>
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Michael Ellerman authored
We haven't updated these for a while it seems, it's nice to have in the oops output. Signed-off-by:
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Michael Ellerman authored
The spec says it "may be problematic" if CPU x registers the VPA of CPU y. Add a warning in case we ever do that. Signed-off-by:
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Michael Ellerman authored
People have been dropping things in here without updating the index, do it for them. Signed-off-by:
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Anton Blanchard authored
The VSX alignment handler needs to write out the existing VSX state to memory before operating on it (flush_vsx_to_thread()). If we take a VSX alignment exception in the kernel bad things will happen. It looks like we could write the kernel state out to the user process, or we could handle the kernel exception using data from the user process (depending if MSR_VSX is set or not). Worse still, if the code to read or write the VSX state causes an alignment exception, we will recurse forever. I ended up with hundreds of megabytes of kernel stack to look through as a result. Floating point and SPE code have similar issues but already include a user check. Add the same check to emulate_vsx(). With this patch any unaligned VSX loads and stores in the kernel will show up as a clear oops rather than silent corruption of kernel or userspace VSX state, or worse, corruption of a potentially unlimited amount of kernel memory. Signed-off-by:
Anton Blanchard <anton@samba.org> Signed-off-by:
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Deepthi Dharwar authored
As a part of pseries_idle backend driver cleanup to make the code common to both pseries and powernv platforms, it is necessary to move the backend-driver code to drivers/cpuidle. As a pre-requisite for that, it is essential to move plpar_wrapper.h to include/asm. Signed-off-by:
Deepthi Dharwar <deepthi@linux.vnet.ibm.com> Signed-off-by:
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Deepthi Dharwar authored
As a part of pseries_idle cleanup to make the backend driver code common to both pseries and powernv. Remove non-essential smt_snooze_delay declaration in pseries.h header file and pseries.h file inclusion in pseries/processor_idle.c Signed-off-by:
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Tom Musta authored
The stmw instruction was incorrectly decoded as an update form instruction and thus the RA register was being clobbered. Also, the utility routine to write memory to unaligned addresses breaks the operation into smaller aligned accesses but was incorrectly incrementing the address by only one; it needs to increment the address by the size of the smaller aligned chunk. Signed-off-by:
Tom Musta <tmusta@us.ibm.com> Signed-off-by:
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Nathan Fontenot authored
Memory I/O resources need to be marked as busy or else we cannot remove them when doing memory hot remove. Signed-off-by:
Nathan Fontenot <nfont@linux.vnet.ibm.com> Signed-off-by:
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Benjamin Herrenschmidt authored
Latest FSL updates from Scott: << Highlights include changes in compiler flag settings on e500 family cores, booke64 hibernation support, support for two new boards, and an erratum workaround. >>
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- 24 Aug, 2013 6 commits
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Mingkai Hu authored
C293PCIE board is a series of Freescale PCIe add-in cards to perform as public key crypto accelerator or secure key management module. - 512KB platform SRAM in addition to 512K L2 Cache/SRAM - 512MB soldered DDR3 32bit memory - CPLD System Logic - 64MB x16 NOR flash and 4GB x8 NAND flash - 16MB SPI flash Signed-off-by:
Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by:
Po Liu <Po.Liu@freescale.com> Signed-off-by:
Scott Wood <scottwood@freescale.com>
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Mingkai Hu authored
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Mingkai Hu authored
Add device tree for SEC 6.0 used on C29x silicon. Signed-off-by:
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Wang Dongsheng authored
Update the 64-bit hibernation code to support Book E CPUs. Some registers and instructions are not defined for Book3e (SDR reg, tlbia instruction). SDR: Storage Description Register. Book3S and Book3E have different address translation mode, we do not need HTABORG & HTABSIZE to translate virtual address to real address. More registers are saved in BookE-64bit.(TCR, SPRG1) Signed-off-by:
Wang Dongsheng <dongsheng.wang@freescale.com> Signed-off-by:
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Chunhe Lan authored
P1023RDB Specification: ----------------------- Memory subsystem: 512MB DDR3 (Fixed DDR on board) 64MB NOR flash 128MB NAND flash Ethernet: eTSEC1: Connected to Atheros AR8035 GETH PHY eTSEC2: Connected to Atheros AR8035 GETH PHY PCIe: Three mini-PCIe slots USB: Two USB2.0 Type A ports I2C: AT24C08 8K Board EEPROM (8 bit address) Signed-off-by:
Chunhe Lan <Chunhe.Lan@freescale.com> Cc: Scott Wood <scottwood@freescale.com> Signed-off-by:
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Haijun.Zhang authored
Add this file to help detect cpu type in runtime. These macros will be more favorable for driver to apply errata and workaround to specified cpu type. Signed-off-by:
Haijun Zhang <Haijun.Zhang@freescale.com> Signed-off-by:
Zhao Chenhui <chenhui.zhao@freescale.com> Signed-off-by:
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- 21 Aug, 2013 4 commits
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Scott Wood authored
Unlike 64-bit, we don't currently support multiplatform between e500 and non-e500, so the -mcpu is not configurable at this time. -msoft-float is specified when testing for -mcpu=8540 because otherwise some older toolchains will fail with "error: E500 and FPRs not supported". Signed-off-by: -
Scott Wood authored
By default use -mcpu=powerpc64 rather than -mtune=power7 Add options for e5500/e6500, with fallbacks for older compilers. Hide the POWER cpu options in booke configs. Signed-off-by: -
Scott Wood authored
This caused lwsync to be converted to sync on 64-bit (on 32-bit lwsync is generated at runtime, and so wasn't affected). Not using lwsync caused a significant slowdown on certain workloads. Setting this flag for any e500-enabled build is also not friendly to multiplatform kernels. Signed-off-by: -
Scott Wood authored
Some CPUs (such as e500v1/v2) don't implement mftb and will take a trap. mfspr should work on everything that has a timebase, and is the preferred instruction according to ISA v2.06. Currently we get away with mftb on 85xx because the assembler converts it to mfspr due to -Wa,-me500. However, that flag has other effects that are undesireable for certain targets (e.g. lwsync is converted to sync), and is hostile to multiplatform kernels. Thus we would like to stop setting it for all e500-family builds. mftb/mftbu instances which are in 85xx code or common code are converted. Instances which will never run on 85xx are left alone. Signed-off-by:
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- 20 Aug, 2013 1 commit
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Scott Wood authored
Erratum A-006598 says that 64-bit mftb is not atomic -- it's subject to a similar race condition as doing mftbu/mftbl on 32-bit. The lower half of timebase is updated before the upper half; thus, we can share the workaround for a similar bug on Cell. This workaround involves looping if the lower half of timebase is zero, thus avoiding the need for a scratch register (other than CR0). This workaround must be avoided when the timebase is frozen, such as during the timebase sync code. This deals with kernel and vdso accesses, but other userspace accesses will of course need to be fixed elsewhere. Signed-off-by:
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- 16 Aug, 2013 1 commit
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Benjamin Herrenschmidt authored
When reworking udbg_16550.c I forgot to remove the old and now useless code for the CONFIG_PPC_EARLY_DEBUG_WSP case, which doesn't build as a result. I also missed a cast. Signed-off-by:
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- 14 Aug, 2013 18 commits
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Anton Blanchard authored
Our ppc64 spinlocks and rwlocks use a trick where a lock token and the paca index are placed in the lock with a single store. Since we are using two u16s they need adjusting for little endian. Signed-off-by:
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Anton Blanchard authored
We need to set ELF_DATA correctly on LE coredumps. Signed-off-by:
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Anton Blanchard authored
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Anton Blanchard authored
Add little endian support for demuxing SMP IPIs Signed-off-by:
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Anton Blanchard authored
Alistair noticed we got a SIGILL on userspace mfpvr instructions. Remove the little endian check in the emulation code, it is probably there to protect against the old pseudo little endian implementations but doesn't make sense for real little endian. Signed-off-by:
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Anton Blanchard authored
The lppaca, slb_shadow and dtl_entry hypervisor structures are big endian, so we have to byte swap them in little endian builds. LE KVM hosts will also need to be fixed but for now add an #error to remind us. Signed-off-by:
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Anton Blanchard authored
Add endian annotation to various hypervisor structures which are defined as big endian. Signed-off-by:
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Alistair Popple authored
The device tree is big endian so make sure we byteswap on little endian. We assume any pHyp calls also return big endian results in memory. Signed-off-by:
Alistair Popple <alistair@popple.id.au> Signed-off-by:
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Alistair Popple authored
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Anton Blanchard authored
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Anton Blanchard authored
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Anton Blanchard authored
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Anton Blanchard authored
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Benjamin Herrenschmidt authored
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Anton Blanchard authored
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Anton Blanchard authored
We pass dma_window to of_parse_dma_window as a void * and then run through hoops to cast it back to a u32 array. In the process we lose endian annotation. Simplify it by just passing a __be32 * down. Signed-off-by:
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Anton Blanchard authored
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Anton Blanchard authored
Fix a couple of sparse warnings. Signed-off-by:
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