- 22 Apr, 2021 4 commits
-
-
Jianqun Xu authored
The mux route tables take many lines for each SoC, and it will be more instances for newly SoC, that makes the file size increase larger. This patch only do coding style for mux route struct, by adding a new definition and replace the structs by script which supplied by huangtao@rock-chips.com sed -i -e " /static struct rockchip_mux_route_data /bcheck b :append-next-line N :check /^[^;]*$/bappend-next-line s/[[:blank:]]*.bank_num = \([[:digit:]]*,\)\n/\tRK_MUXROUTE_SAME(\1/g s/[[:blank:]]*.pin =[[:blank:]]*0,\n/ RK_PA0,/g s/[[:blank:]]*.pin =[[:blank:]]*1,\n/ RK_PA1,/g s/[[:blank:]]*.pin =[[:blank:]]*2,\n/ RK_PA2,/g s/[[:blank:]]*.pin =[[:blank:]]*3,\n/ RK_PA3,/g s/[[:blank:]]*.pin =[[:blank:]]*4,\n/ RK_PA4,/g s/[[:blank:]]*.pin =[[:blank:]]*5,\n/ RK_PA5,/g s/[[:blank:]]*.pin =[[:blank:]]*6,\n/ RK_PA6,/g s/[[:blank:]]*.pin =[[:blank:]]*7,\n/ RK_PA7,/g s/[[:blank:]]*.pin =[[:blank:]]*8,\n/ RK_PB0,/g s/[[:blank:]]*.pin =[[:blank:]]*9,\n/ RK_PB1,/g s/[[:blank:]]*.pin =[[:blank:]]*10,\n/ RK_PB2,/g s/[[:blank:]]*.pin =[[:blank:]]*11,\n/ RK_PB3,/g s/[[:blank:]]*.pin =[[:blank:]]*12,\n/ RK_PB4,/g s/[[:blank:]]*.pin =[[:blank:]]*13,\n/ RK_PB5,/g s/[[:blank:]]*.pin =[[:blank:]]*14,\n/ RK_PB6,/g s/[[:blank:]]*.pin =[[:blank:]]*15,\n/ RK_PB7,/g s/[[:blank:]]*.pin =[[:blank:]]*16,\n/ RK_PC0,/g s/[[:blank:]]*.pin =[[:blank:]]*17,\n/ RK_PC1,/g s/[[:blank:]]*.pin =[[:blank:]]*18,\n/ RK_PC2,/g s/[[:blank:]]*.pin =[[:blank:]]*19,\n/ RK_PC3,/g s/[[:blank:]]*.pin =[[:blank:]]*20,\n/ RK_PC4,/g s/[[:blank:]]*.pin =[[:blank:]]*21,\n/ RK_PC5,/g s/[[:blank:]]*.pin =[[:blank:]]*22,\n/ RK_PC6,/g s/[[:blank:]]*.pin =[[:blank:]]*23,\n/ RK_PC7,/g s/[[:blank:]]*.pin =[[:blank:]]*24,\n/ RK_PD0,/g s/[[:blank:]]*.pin =[[:blank:]]*25,\n/ RK_PD1,/g s/[[:blank:]]*.pin =[[:blank:]]*26,\n/ RK_PD2,/g s/[[:blank:]]*.pin =[[:blank:]]*27,\n/ RK_PD3,/g s/[[:blank:]]*.pin =[[:blank:]]*28,\n/ RK_PD4,/g s/[[:blank:]]*.pin =[[:blank:]]*29,\n/ RK_PD5,/g s/[[:blank:]]*.pin =[[:blank:]]*30,\n/ RK_PD6,/g s/[[:blank:]]*.pin =[[:blank:]]*31,\n/ RK_PD7,/g s/[[:blank:]]*.func = \([[:digit:]]*,\)\n/ \1/g s/[[:blank:]]*.route_location =[[:blank:]]*\([[:print:]]*,\)\n//g s/[[:blank:]]*.route_offset = \(0x[[:xdigit:]]*,\)\n/ \1/g s/[[:blank:]]*.route_val =[[:blank:]]*\([[:print:]]*\),\n/ \1),/g s/\t{\n//g s/\t}, {\n//g s/\t},//g s/[[:blank:]]*\(\/\*[[:print:]]*\*\/\)\n[[:blank:]]*RK_MUXROUTE_SAME(\([[:print:]]*\)),\n/\tRK_MUXROUTE_SAME(\2), \1\n/g s/[[:blank:]]*\(\/\*[[:print:]]*\*\/\)\n[[:blank:]]*RK_MUXROUTE_SAME(\([[:print:]]*\)),/\tRK_MUXROUTE_SAME(\2), \1\n/g " drivers/pinctrl/pinctrl-rockchip.c Reviewed-by:Heiko Stuebner <heiko@sntech.de> Signed-off-by:
Jianqun Xu <jay.xu@rock-chips.com> Link: https://lore.kernel.org/r/20210420091240.1246429-1-jay.xu@rock-chips.comSigned-off-by:
Linus Walleij <linus.walleij@linaro.org>
-
Andy Shevchenko authored
It seems that we will have more and more pin controllers that support PWM function on the (selected) pins. Due to it being a part of pin controller IP the idea is to have some code that will switch the mode and attach the corresponding driver, for example, via using it as a library. Meanwhile, put a corresponding item to the pin_config_param enumerator. Signed-off-by:
Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20210412140741.39946-3-andriy.shevchenko@linux.intel.comSigned-off-by:
-
Andy Shevchenko authored
Better to have a MODE group of settings to keep them together when ordered alphabetically. Hence, rename PIN_CONFIG_LOW_POWER_MODE to PIN_CONFIG_MODE_LOW_POWER. Signed-off-by:
-
Andy Shevchenko authored
It seems the ordering is by name. Keep it that way. Signed-off-by:
-
- 21 Apr, 2021 18 commits
-
-
Sai Krishna Potthuri authored
Adding documentation and dt-bindings file which contains MIO pin configuration defines for Xilinx ZynqMP pinctrl driver. Signed-off-by:
Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com> Reviewed-by:
Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/1618485193-5403-3-git-send-email-lakshmi.sai.krishna.potthuri@xilinx.comSigned-off-by:
-
Andy Shevchenko authored
The kernel doc string mistakenly advertises the pin_get_name_from_id(). Fix it, otherwise kernel doc validator is not happy: .../core.c:168: warning: expecting prototype for pin_get_name_from_id(). Prototype was for pin_get_name() instead Fixes: dcb5dbc3 ("pinctrl: show pin name for pingroups in sysfs") Cc: Dong Aisheng <dong.aisheng@linaro.org> Signed-off-by:
-
Tzung-Bi Shih authored
Commit 42a46434 ("pinctrl: add lock in mtk_rmw function.") uses mutex lock in mtk_rmw. However the function is possible called from atomic context. For example call trace: mutex_lock+0x28/0x64 mtk_rmw+0x38/0x80 [snip] max98357a_daiops_trigger+0x8c/0x9c soc_pcm_trigger+0x5c/0x10c The max98357a_daiops_trigger() could run in either atomic or non-atomic context. As a result, dmesg shows some similar messages: "BUG: sleeping function called from invalid context at kernel/locking/mutex.c:254". Uses spin lock in mtk_rmw instead. Fixes: 42a46434 ("pinctrl: add lock in mtk_rmw function.") Signed-off-by:
Tzung-Bi Shih <tzungbi@google.com> Link: https://lore.kernel.org/r/20210419093449.3125704-1-tzungbi@google.comSigned-off-by:
-
Zhiyong Tao authored
This patch provides the advanced drive raw data setting version for I2C used pins on MT8195. Signed-off-by:
Zhiyong Tao <zhiyong.tao@mediatek.com> Acked-by:
Sean Wang <sean.wang@kernel.org> Link: https://lore.kernel.org/r/20210413055702.27535-4-zhiyong.tao@mediatek.comSigned-off-by:
-
Zhiyong Tao authored
This commit includes pinctrl driver for mt8195. Signed-off-by:
-
Zhiyong Tao authored
1. This patch adds pinctrl file for mt8195. 2. This patch adds mt8195 compatible node in binding document. Signed-off-by:
-
周琰杰 (Zhou Yanjie) authored
Add support for probing the pinctrl-ingenic driver on the X2000 SoC from Ingenic. Signed-off-by:
周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Reviewed-by:
Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by:
Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/1618757073-1724-13-git-send-email-zhouyanjie@wanyeetech.comSigned-off-by:
-
周琰杰 (Zhou Yanjie) authored
Add support for probing the pinctrl-ingenic driver on the JZ4775 SoC from Ingenic. Signed-off-by:
-
周琰杰 (Zhou Yanjie) authored
Add support for probing the pinctrl-ingenic driver on the JZ4755 SoC from Ingenic. Signed-off-by:
-
周琰杰 (Zhou Yanjie) authored
Add support for probing the pinctrl-ingenic driver on the JZ4750 SoC from Ingenic. Signed-off-by:
-
周琰杰 (Zhou Yanjie) authored
Add support for probing the pinctrl-ingenic driver on the JZ4730 SoC from Ingenic. This driver is derived from Paul Boddie. It is worth to noting that the JZ4730 SoC is special in having two control registers (upper/lower), so add code to handle the JZ4730 specific register offsets and some register pairs which have 2 bits for each GPIO pin. Tested-by: H. Nikolaus Schaller <hns@goldelico.com> # on Letux400 Co-developed-by:
Paul Boddie <paul@boddie.org.uk> Signed-off-by:
H. Nikolaus Schaller <hns@goldelico.com> Signed-off-by:
-
周琰杰 (Zhou Yanjie) authored
Add the pinctrl bindings for the JZ4730 SoC, the JZ4750 SoC, the JZ4755 SoC, the JZ4775 SoC and the X2000 SoC from Ingenic. Signed-off-by:
-
周琰杰 (Zhou Yanjie) authored
1.Move the "INGENIC_PIN_GROUP_FUNCS" to the macro definition section. 2.Add tabs before values to align the code in the macro definition section. Signed-off-by:
-
周琰杰 (Zhou Yanjie) authored
1.Add DMIC pins support for the JZ4780 SoC. 2.Add DMIC pins support for the X1000 SoC. 3.Add DMIC pins support for the X1500 SoC. 4.Add DMIC pins support for the X1830 SoC. Signed-off-by:
-
周琰杰 (Zhou Yanjie) authored
1.In the JZ4740 part, remove pointless "lcd-no-pins", use "lcd-special" and "lcd-generic" instead "lcd-18bit-tft". Currently, in the mainline, no other devicetree out there is using the "lcd-18bit-tft" ABI, so we should be able to replace it safely. 2.In the JZ4725B part, adjust the location of the LCD pins related code to keep them consistent with the style of other parts. 3.In the JZ4760 part, add the missing comma and adjust element order in "jz4760_lcd_special_pins[]", keep them in the order of CLS/SPL/PS/REV like other "lcd_special_pins" arrays. And adjust the location of the "jz4760_lcd_generic" related code to keep them consistent with the style of other parts. 4.In the JZ4770 part, remove pointless "lcd-no-pins", add the missing "lcd-16bit", "lcd-18bit", "lcd-special", "lcd-generic". 5.In the X1000 part and the X1500 part, remove pointless "lcd-no-pins". 6.In the X1830 part, replace "lcd-rgb-18bit" with "lcd-tft-8bit" and "lcd-tft-24bit", because of the description of the TRANS_CONFIG.MODE register bits in the PM manual of the X1830, shows that the X1830 only supppots 24bit mode and 8bit mode for tft interface, only 18 pins in the GPIO table are because of the data[17:16], the data[9:8], and the data[1:0] has not been connected. And according to the description, the two interfaces supported by X1830 are respectively referred to as "TFT interface" and "SLCD interface", so the "lcd-rgb-xxx" is replaced with "lcd-tft-xxx" to avoid confusion. Signed-off-by:
-
周琰杰 (Zhou Yanjie) authored
Adjust the sequence of X1830's SSI related codes to make it consistent with other Ingenic SoCs. Signed-off-by:
-
周琰杰 (Zhou Yanjie) authored
Add X1830 support in "ingenic_pinconf_get()", so that it can read the configuration of X1830 SoC correctly. Fixes: d7da2a1e ("pinctrl: Ingenic: Add pinctrl driver for X1830.") Cc: <stable@vger.kernel.org> Signed-off-by:
-
周琰杰 (Zhou Yanjie) authored
The MII group of JZ4770's MAC should have 7 pins, add missing pins to the MII group. Fixes: 5de1a73e ("Pinctrl: Ingenic: Add missing parts for JZ4770 and JZ4780.") Cc: <stable@vger.kernel.org> Signed-off-by:
-
- 14 Apr, 2021 2 commits
-
-
Ezequiel Garcia authored
Add RK3568/RK3566 SoC support to pinctrl. Signed-off-by:
Ezequiel Garcia <ezequiel@collabora.com> Reviewed-by:
-
Julian Braha authored
When PINCTRL_MSM is enabled, and GPIOLIB is disabled, Kbuild gives the following warning: WARNING: unmet direct dependencies detected for GPIOLIB_IRQCHIP Depends on [n]: GPIOLIB [=n] Selected by [y]: - PINCTRL_MSM [=y] && PINCTRL [=y] && (ARCH_QCOM || COMPILE_TEST [=y]) This is because PINCTRL_MSM selects GPIOLIB_IRQCHIP, without selecting or depending on GPIOLIB, despite GPIOLIB_IRQCHIP depending on GPIOLIB. Having PINCTRL_MSM select GPIOLIB will cause a recursive dependency error. Signed-off-by:
Julian Braha <julianbraha@gmail.com> Reviewed-by:
Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210414025138.480085-1-julianbraha@gmail.comSigned-off-by:
-
- 13 Apr, 2021 1 commit
-
-
Tudor Ambarus authored
The slew rate was enabled by default for each configuration of the pin. In case the pin had more than one configuration, even if we set the slew rate as disabled in the device tree, the next pin configuration would set again the slew rate enabled by default, overwriting the slew rate disablement. Instead of enabling the slew rate by default for each pin configuration, enable the slew rate by default just once per pin, regardless of the number of configurations. This way the slew rate disablement will also work for cases where pins have multiple configurations. Fixes: c709135e ("pinctrl: at91-pio4: add support for slew-rate") Signed-off-by:
Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by:
Claudiu Beznea <claudiu.beznea@microchip.com> Acked-by:
Ludovic Desroches <ludovic.desroches@microchip.com> Link: https://lore.kernel.org/r/20210409082522.625168-1-tudor.ambarus@microchip.comSigned-off-by:
-
- 10 Apr, 2021 1 commit
-
-
Krzysztof Kozlowski authored
The Special Function Registers on all Exynos SoC, including ARM64, are 32-bit wide, so entire driver uses matching functions like readl() or writel(). On 64-bit ARM using unsigned long for register masks: 1. makes little sense as immediately after bitwise operation it will be cast to 32-bit value when calling writel(), 2. is actually error-prone because it might promote other operands to 64-bit. Addresses-Coverity: Unintentional integer overflow Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Reviewed-by:
Sylwester Nawrocki <s.nawrocki@samsung.com> Link: https://lore.kernel.org/r/20210408195029.69974-1-krzysztof.kozlowski@canonical.comSigned-off-by:
-
- 08 Apr, 2021 9 commits
-
-
Guru Das Srinagesh authored
Add support for the two GPIOs present on Qualcomm Technologies, Inc. PM8008. Reviewed-by:
Guru Das Srinagesh <gurus@codeaurora.org> Link: https://lore.kernel.org/r/129d241ee510e28536d35dbfeee75474e12d8d22.1617901945.git.gurus@codeaurora.orgSigned-off-by:
-
Guru Das Srinagesh authored
Add support for the 2 GPIOs present on Qualcomm Technologies, Inc. PM8008. Acked-by:
-
Niklas Söderlund authored
The error is constructed using the wrong variable. Signed-off-by:
Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/20210328164222.720525-1-niklas.soderlund+renesas@ragnatech.seSigned-off-by:
-
Fabio Estevam authored
Performing the 'unbind' operation on pinctrl drivers is not a sensible usecase, so pass the suppress_bind_attrs atribute to prevent it. Signed-off-by:
Fabio Estevam <festevam@gmail.com> Link: https://lore.kernel.org/r/20210328183034.555702-2-festevam@gmail.comSigned-off-by:
-
Fabio Estevam authored
i.MX is a DT-only platform, so of_match_ptr() can be safely removed. Remove the unneeded of_match_ptr(). Signed-off-by:
-
Junlin Yang authored
when devm_kcalloc fails, use -ENOMEM instead of -EINVAL, and consistent with other devm_kcalloc return values. Signed-off-by:
Junlin Yang <yangjunlin@yulong.com> Link: https://lore.kernel.org/r/20210330062655.1027-1-angkery@163.comSigned-off-by:
-
Jianqun Xu authored
RK3568 SoCs have 5 gpio controllers, each gpio has 32 pins. GPIO supports set iomux, pull, drive strength and schmitt. Signed-off-by:
-
Marek Vasut authored
The "invalid function %d on pin %d .\n" message is triplicated in the driver in different variants, just pull it into the function and have it once in the driver. The bonus is that all variants of the message now print the pin number and AF consistently, so it is easier to debug such pinmux problems. Signed-off-by:
Marek Vasut <marex@denx.de> Cc: Fabien Dessenne <fabien.dessenne@st.com> Cc: Alexandre Torgue <alexandre.torgue@st.com> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Acked-by:
Fabien Dessenne <fabien.dessenne@foss.st.com> Link: https://lore.kernel.org/r/20210406180035.279249-1-marex@denx.deSigned-off-by:
-
Randy Dunlap authored
The additional patch below fixes all of the kconfig warnings and build errors for me. Link: https://lore.kernel.org/r/9e1cec76-1c0a-9203-7995-4c2d09b711d8@infradead.orgSigned-off-by:
Randy Dunlap <rdunlap@infradead.org> [Tweaked some other line in the BCMxxx] Signed-off-by:
-
- 07 Apr, 2021 1 commit
-
-
Linus Walleij authored
Merge tag 'renesas-pinctrl-for-v5.13-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: renesas: Updates for v5.13 (take two) - Add bias support for the R-Car M2-W and M2-N, and RZ/G1M and RZ/G1N SoCs, - Miscellaneous cleanups and improvements.
-
- 31 Mar, 2021 2 commits
-
-
Linus Walleij authored
Add depends on OF so we don't get weird build errors on randconfig. Also order selects the same as the other drivers for pure aestetic reasons. Reported-by:
-
Álvaro Fernández Rojas authored
The current implementation of bcm6362_set_gpio() produces the following warning on x86_64: drivers/pinctrl/bcm/pinctrl-bcm6362.c: In function 'bcm6362_set_gpio': drivers/pinctrl/bcm/pinctrl-bcm6362.c:503:8: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] 503 | (uint32_t) desc->drv_data, 0); | ^ Modify the code to make it similar to bcm63268_set_gpio() in order to fix the warning. Fixes: 705791e2 ("pinctrl: add a pincontrol driver for BCM6362") Signed-off-by:Álvaro Fernández Rojas <noltari@gmail.com> Link: https://lore.kernel.org/r/20210330103225.3949-1-noltari@gmail.comReviewed-by:
-
- 29 Mar, 2021 2 commits
-
-
Linus Walleij authored
-
Linus Walleij authored
Merge tag 'intel-pinctrl-v5.13-1' of gitolite.kernel.org:pub/scm/linux/kernel/git/pinctrl/intel into devel intel-pinctrl for v5.13-1 * Don't disable disabled IRQs in the handler * Fix the base calculation for groups defined by size The following is an automated git shortlog grouped by driver: intel: - No need to disable IRQs in the handler - Show the GPIO base calculation explicitly
-
