Commit ef47d328 authored by Victor Goldenshtein's avatar Victor Goldenshtein Committed by Luciano Coelho

wl18xx: fix boot process in high temperature environment

In addition to existing WCS PLL configuration add and enable
also the coex PLL during init phase. This fixes boot failures
due to silicon latchup in high temperature environment (>85c).
Signed-off-by: default avatarVictor Goldenshtein <victorg@ti.com>
Signed-off-by: default avatarNadim Zubidat <nadimz@ti.com>
Signed-off-by: default avatarEliad Peller <eliad@wizery.com>
Signed-off-by: default avatarLuciano Coelho <luciano.coelho@intel.com>
parent 49540d1b
...@@ -623,6 +623,18 @@ static const int wl18xx_rtable[REG_TABLE_LEN] = { ...@@ -623,6 +623,18 @@ static const int wl18xx_rtable[REG_TABLE_LEN] = {
[REG_RAW_FW_STATUS_ADDR] = WL18XX_FW_STATUS_ADDR, [REG_RAW_FW_STATUS_ADDR] = WL18XX_FW_STATUS_ADDR,
}; };
static const struct wl18xx_clk_cfg wl18xx_clk_table_coex[NUM_CLOCK_CONFIGS] = {
[CLOCK_CONFIG_16_2_M] = { 8, 121, 0, 0, false },
[CLOCK_CONFIG_16_368_M] = { 8, 120, 0, 0, false },
[CLOCK_CONFIG_16_8_M] = { 8, 117, 0, 0, false },
[CLOCK_CONFIG_19_2_M] = { 10, 128, 0, 0, false },
[CLOCK_CONFIG_26_M] = { 11, 104, 0, 0, false },
[CLOCK_CONFIG_32_736_M] = { 8, 120, 0, 0, false },
[CLOCK_CONFIG_33_6_M] = { 8, 117, 0, 0, false },
[CLOCK_CONFIG_38_468_M] = { 10, 128, 0, 0, false },
[CLOCK_CONFIG_52_M] = { 11, 104, 0, 0, false },
};
static const struct wl18xx_clk_cfg wl18xx_clk_table[NUM_CLOCK_CONFIGS] = { static const struct wl18xx_clk_cfg wl18xx_clk_table[NUM_CLOCK_CONFIGS] = {
[CLOCK_CONFIG_16_2_M] = { 7, 104, 801, 4, true }, [CLOCK_CONFIG_16_2_M] = { 7, 104, 801, 4, true },
[CLOCK_CONFIG_16_368_M] = { 9, 132, 3751, 4, true }, [CLOCK_CONFIG_16_368_M] = { 9, 132, 3751, 4, true },
...@@ -704,6 +716,23 @@ static int wl18xx_set_clk(struct wl1271 *wl) ...@@ -704,6 +716,23 @@ static int wl18xx_set_clk(struct wl1271 *wl)
wl18xx_clk_table[clk_freq].p, wl18xx_clk_table[clk_freq].q, wl18xx_clk_table[clk_freq].p, wl18xx_clk_table[clk_freq].q,
wl18xx_clk_table[clk_freq].swallow ? "swallow" : "spit"); wl18xx_clk_table[clk_freq].swallow ? "swallow" : "spit");
/* coex PLL configuration */
ret = wl18xx_top_reg_write(wl, PLLSH_COEX_PLL_N,
wl18xx_clk_table_coex[clk_freq].n);
if (ret < 0)
goto out;
ret = wl18xx_top_reg_write(wl, PLLSH_COEX_PLL_M,
wl18xx_clk_table_coex[clk_freq].m);
if (ret < 0)
goto out;
/* bypass the swallowing logic */
ret = wl18xx_top_reg_write(wl, PLLSH_COEX_PLL_SWALLOW_EN,
PLLSH_COEX_PLL_SWALLOW_EN_VAL1);
if (ret < 0)
goto out;
ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_N, ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_N,
wl18xx_clk_table[clk_freq].n); wl18xx_clk_table[clk_freq].n);
if (ret < 0) if (ret < 0)
...@@ -745,6 +774,30 @@ static int wl18xx_set_clk(struct wl1271 *wl) ...@@ -745,6 +774,30 @@ static int wl18xx_set_clk(struct wl1271 *wl)
PLLSH_WCS_PLL_SWALLOW_EN_VAL2); PLLSH_WCS_PLL_SWALLOW_EN_VAL2);
} }
/* choose WCS PLL */
ret = wl18xx_top_reg_write(wl, PLLSH_WL_PLL_SEL,
PLLSH_WL_PLL_SEL_WCS_PLL);
if (ret < 0)
goto out;
/* enable both PLLs */
ret = wl18xx_top_reg_write(wl, PLLSH_WL_PLL_EN, PLLSH_WL_PLL_EN_VAL1);
if (ret < 0)
goto out;
udelay(1000);
/* disable coex PLL */
ret = wl18xx_top_reg_write(wl, PLLSH_WL_PLL_EN, PLLSH_WL_PLL_EN_VAL2);
if (ret < 0)
goto out;
/* reset the swallowing logic */
ret = wl18xx_top_reg_write(wl, PLLSH_COEX_PLL_SWALLOW_EN,
PLLSH_COEX_PLL_SWALLOW_EN_VAL2);
if (ret < 0)
goto out;
out: out:
return ret; return ret;
} }
......
...@@ -114,6 +114,11 @@ ...@@ -114,6 +114,11 @@
#define PLATFORM_DETECTION 0xA0E3E0 #define PLATFORM_DETECTION 0xA0E3E0
#define OCS_EN 0xA02080 #define OCS_EN 0xA02080
#define PRIMARY_CLK_DETECT 0xA020A6 #define PRIMARY_CLK_DETECT 0xA020A6
#define PLLSH_COEX_PLL_N 0xA02384
#define PLLSH_COEX_PLL_M 0xA02382
#define PLLSH_COEX_PLL_SWALLOW_EN 0xA0238E
#define PLLSH_WL_PLL_SEL 0xA02398
#define PLLSH_WCS_PLL_N 0xA02362 #define PLLSH_WCS_PLL_N 0xA02362
#define PLLSH_WCS_PLL_M 0xA02360 #define PLLSH_WCS_PLL_M 0xA02360
#define PLLSH_WCS_PLL_Q_FACTOR_CFG_1 0xA02364 #define PLLSH_WCS_PLL_Q_FACTOR_CFG_1 0xA02364
...@@ -128,9 +133,17 @@ ...@@ -128,9 +133,17 @@
#define PLLSH_WCS_PLL_P_FACTOR_CFG_1_MASK 0xFFFF #define PLLSH_WCS_PLL_P_FACTOR_CFG_1_MASK 0xFFFF
#define PLLSH_WCS_PLL_P_FACTOR_CFG_2_MASK 0x000F #define PLLSH_WCS_PLL_P_FACTOR_CFG_2_MASK 0x000F
#define PLLSH_WL_PLL_EN_VAL1 0x7
#define PLLSH_WL_PLL_EN_VAL2 0x2
#define PLLSH_COEX_PLL_SWALLOW_EN_VAL1 0x2
#define PLLSH_COEX_PLL_SWALLOW_EN_VAL2 0x11
#define PLLSH_WCS_PLL_SWALLOW_EN_VAL1 0x1 #define PLLSH_WCS_PLL_SWALLOW_EN_VAL1 0x1
#define PLLSH_WCS_PLL_SWALLOW_EN_VAL2 0x12 #define PLLSH_WCS_PLL_SWALLOW_EN_VAL2 0x12
#define PLLSH_WL_PLL_SEL_WCS_PLL 0x0
#define PLLSH_WL_PLL_SEL_COEX_PLL 0x1
#define WL18XX_REG_FUSE_DATA_1_3 0xA0260C #define WL18XX_REG_FUSE_DATA_1_3 0xA0260C
#define WL18XX_PG_VER_MASK 0x70 #define WL18XX_PG_VER_MASK 0x70
#define WL18XX_PG_VER_OFFSET 4 #define WL18XX_PG_VER_OFFSET 4
......
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