Adding the #address-cells/#size-cells properties without also
adding the other required properties for PCI nodes causes new
build warnings from dtc that now show up everywhere, rather than
just while verifying the yaml bindings:

arch/arm/boot/dts/bcm5301x.dtsi:240.21-246.5: Warning (pci_bridge): /axi@18000000/pcie@12000: missing ranges for PCI bridge (or not a bridge)
arch/arm/boot/dts/bcm5301x.dtsi:248.21-254.5: Warning (pci_bridge): /axi@18000000/pcie@13000: missing ranges for PCI bridge (or not a bridge)
arch/arm/boot/dts/bcm5301x.dtsi:256.21-262.5: Warning (pci_bridge): /axi@18000000/pcie@14000: missing ranges for PCI bridge (or not a bridge)
arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dtb: Warning (unit_address_format): Failed prerequisite 'pci_bridge'

Revert it for now.

Fixes: 61dc1e38 ("ARM: dts: BCM5301X: Add basic PCI controller properties")
Reported-by: Stephen Rothwell <sfr@canb.auug.org.au>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Merge tag 'samsung-dt-dt64-6.1-2' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/dt

Samsung DTS ARM and ARM64 changes for v6.1

Late cleanup and fixes for Samsung DTS:
1. Fix polarity of pins:
   - enable GPIO of NFC chip in Exynos5433 TM2 boards,
   - vbus GPIO of EHCI in Exynos4412 Origen board.
2. Correct name of pin configuration nodes - redundant "pins" in the
   name (no functional impact).

* tag 'samsung-dt-dt64-6.1-2' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
  ARM: dts: s5pv210: correct double "pins" in pinmux node
  ARM: dts: exynos: fix polarity of VBUS GPIO of Origen
  arm64: dts: exynos: fix polarity of "enable" line of NFC chip in TM2

Link: https://lore.kernel.org/r/20221003073916.12588-1-krzysztof.kozlowski@linaro.orgSigned-off-by: Arnd Bergmann <arnd@arndb.de>

Drop second "pins" suffix from pin configuration/mux nodes.

Link: https://lore.kernel.org/r/20220926125824.477920-1-krzysztof.kozlowski@linaro.orgSigned-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

EHCI Oxynos (drivers/usb/host/ehci-exynos.c) drives VBUS GPIO high when
trying to power up the bus, therefore the GPIO in DTS must be marked as
"active high". This will be important when EHCI driver is converted to
gpiod API that respects declared polarities.

Fixes: 4e8991de ("ARM: dts: exynos: Enable AX88760 USB hub on Origen board")
Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Link: https://lore.kernel.org/r/20220927220504.3744878-1-dmitry.torokhov@gmail.comSigned-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

According to s3fwrn5 driver code the "enable" GPIO line is driven "high"
when chip is not in use (mode is S3FWRN5_MODE_COLD), and is driven "low"
when chip is in use.

s3fwrn5_phy_power_ctrl():

	...
	gpio_set_value(phy->gpio_en, 1);
	...
	if (mode != S3FWRN5_MODE_COLD) {
		msleep(S3FWRN5_EN_WAIT_TIME);
		gpio_set_value(phy->gpio_en, 0);
		msleep(S3FWRN5_EN_WAIT_TIME);
	}

Therefore the line described by "en-gpios" property should be annotated
as "active low".

The wakeup gpio appears to have correct polarity (active high).
Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Link: https://lore.kernel.org/r/20220929011557.4165216-1-dmitry.torokhov@gmail.comSigned-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Updates from Kunihiko Hayashi via email:

 "Update devicetree sources for UniPhier armv8 SoCs to remove dtschema
  warnings, add support existing features that haven't yet been
  described, and replace constants with macros."

* uniphier/dt:
  arm64: dts: uniphier: Add L2 cache node
  arm64: dts: uniphier: Remove compatible "snps,dw-pcie" from pcie node
  arm64: dts: uniphier: Fix opp-table node name for LD20
  arm64: dts: uniphier: Add USB-device support for PXs3 reference board
  arm64: dts: uniphier: Add ahci controller nodes for PXs3
  arm64: dts: uniphier: Use GIC interrupt definitions
  arm64: dts: uniphier: Rename gpio-hog nodes
  arm64: dts: uniphier: Rename usb-glue node for USB3 to usb-controller
  arm64: dts: uniphier: Rename usb-phy node for USB2 to usb-controller
  arm64: dts: uniphier: Rename pvtctl node to thermal-sensor
  ARM: dts: uniphier: Remove compatible "snps,dw-pcie-ep" from pcie-ep node
  ARM: dts: uniphier: Move interrupt-parent property to each child node in uniphier-support-card
  ARM: dts: uniphier: Add ahci controller nodes for PXs2
  ARM: dts: uniphier: Add ahci controller nodes for Pro4
  ARM: dts: uniphier: Use GIC interrupt definitions
  ARM: dts: uniphier: Rename gpio-hog node
  ARM: dts: uniphier: Rename usb-glue node for USB3 to usb-controller
  ARM: dts: uniphier: Rename usb-phy node for USB2 to usb-controller
  ARM: dts: uniphier: Rename pvtctl node to thermal-sensor

Add a L2 cache node referenced from CPU nodes as the missing cache hierarchy
information because the following warning was issued.

  cacheinfo: Unable to detect cache hierarchy for CPU 0
  Early cacheinfo failed, ret = -2
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Link: https://lore.kernel.org/r/20220913042321.4817-11-hayashi.kunihiko@socionext.com'
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

The generic platform driver pcie-designware-plat.c doesn't work for
UniPhier PCIe host controller, because the controller has some
necessary initialization sequence for the controller-specific logic.

Currently the controller doesn't use "snps,dw-pcie" compatible,
so this is no longer needed. Remove the compatible string from the
pcie node.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Link: https://lore.kernel.org/r/20220913042321.4817-10-hayashi.kunihiko@socionext.com'
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

To fix dtbs_check warning:

uniphier-ld20-akebi96.dt.yaml: opp-table0: $nodename:0: 'opp-table0' does not match '^opp-table(-[a-z0-9]+)?$'
        From schema: Documentation/devicetree/bindings/opp/opp-v2.yaml
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Link: https://lore.kernel.org/r/20220913042321.4817-9-hayashi.kunihiko@socionext.com'
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

PXs3 reference board can change each USB port 0 and 1 to device mode
with jumpers. Prepare devicetree sources for USB port 0 and 1.

This specifies dr_mode, pinctrl, and some quirks and removes nodes for
unused phys and vbus-supply properties.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Link: https://lore.kernel.org/r/20220913042321.4817-8-hayashi.kunihiko@socionext.com'
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Add ahci core controller and glue layer nodes including reset-controller
and sata-phy.

This supports for PXs3 and the boards.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Link: https://lore.kernel.org/r/20220913042321.4817-7-hayashi.kunihiko@socionext.com'
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Use human-readable definitions for GIC interrupt type and flag, instead of
hard-coding the numbers. No functional change.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Link: https://lore.kernel.org/r/20220913042321.4817-6-hayashi.kunihiko@socionext.com'
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

According to gpio-hog schema, should add the suffix "-hog" to the node
names including gpio-hog to fix the following warning.

  uniphier-ld11-ref.dtb: gpio@55000000: 'xirq0' does not match any of the regexes: '^.+-hog(-[0-9+)?$', 'pinctrl-[0-9]+'
      From schema: Documentation/devicetree/bindings/gpio/socionext,uniphier-gpio.yaml

This applies to the devicetre for LD11, LD20 and PXs3 SoCs.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Link: https://lore.kernel.org/r/20220913042321.4817-5-hayashi.kunihiko@socionext.com'
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

This "usb-glue" stands for an external controller associated with USB core,
however, this is not common. So rename to "usb-controller".
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Link: https://lore.kernel.org/r/20220913042321.4817-4-hayashi.kunihiko@socionext.com'
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Actual phy nodes are each child node. The parent node should be
usb-controller node as a representation of the phy integration.
This applies to the devicetree for LD11 SoC.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Link: https://lore.kernel.org/r/20220913042321.4817-3-hayashi.kunihiko@socionext.com'
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

The pvtctl node belongs to thermal-sensor, so the node name should be
renamed to thermal-sensor.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Link: https://lore.kernel.org/r/20220913042321.4817-2-hayashi.kunihiko@socionext.com'
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

The generic platform driver pcie-designware-plat.c doesn't work for
UniPhier PCIe endpoint controller, because the controller has some
necessary initialization sequence for the controller-specific logic.

Currently the controller doesn't use "snps,dw-pcie-ep" compatible,
so this is no longer needed. Remove the compatible string from the
pcie-ep node.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Link: https://lore.kernel.org/r/20220913042249.4708-10-hayashi.kunihiko@socionext.com'
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

The dtschema warning:
  uniphier-ld11-ref.dt.yaml: system-bus@58c00000: 'interrupt-parent' does not
  match any of the regexes: '^.*@[1-5],[1-9a-f][0-9a-f]+$', 'pinctrl-[0-9]+'
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Link: https://lore.kernel.org/r/20220913042249.4708-9-hayashi.kunihiko@socionext.com'
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Add ahci core controller and glue layer nodes including reset-controller
and sata-phy.

This supports for PXs2 and the boards without PXs2 vodka board that
doesn't implement any SATA connectors.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Link: https://lore.kernel.org/r/20220913042249.4708-8-hayashi.kunihiko@socionext.com'
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Add ahci controller, glue layer, and clock nodes for Pro4 SoC. The glue
layer includes reset and phy, and the clock node is used for handling ahci
clocks on SoC-glue.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Link: https://lore.kernel.org/r/20220913042249.4708-7-hayashi.kunihiko@socionext.com'
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Use human-readable definitions for GIC interrupt type and flag, instead of
hard-coding the numbers. No functional change.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Link: https://lore.kernel.org/r/20220913042249.4708-6-hayashi.kunihiko@socionext.com'
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

According to gpio-hog schema, should add the suffix "-hog" to the node
names including gpio-hog to fix the following warning.

  uniphier-pro4-ref.dtb: gpio@55000000: 'xirq2' does not match any of the regexes: '^.+-hog(-[0-9+)?$', 'pinctrl-[0-9]+'
      From schema: Documentation/devicetree/bindings/gpio/socionext,uniphier-gpio.yaml

This applies to the devicetree for LD4, LD6b, Pro4 and sLD8 SoCs.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Link: https://lore.kernel.org/r/20220913042249.4708-5-hayashi.kunihiko@socionext.com'
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

This "usb-glue" stands for an external controller associated with USB core,
however, this is not common. So rename to "usb-controller".
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Link: https://lore.kernel.org/r/20220913042249.4708-4-hayashi.kunihiko@socionext.com'
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Actual phy nodes are each child node. The parent node should be
usb-controller node as a representation of the phy integration.
This applies to the devicetree for Pro4 SoC.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Link: https://lore.kernel.org/r/20220913042249.4708-3-hayashi.kunihiko@socionext.com'
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

The pvtctl node belongs to thermal-sensor, so the node name should be
renamed to thermal-sensor.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Link: https://lore.kernel.org/r/20220913042249.4708-2-hayashi.kunihiko@socionext.com'
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

According to s5k6a3 driver code, the reset line for the chip appears to
be active low. This also matches the typical polarity of reset lines in
general. Let's fix it up as having correct polarity in DTS is important
when the driver will be switched over to gpiod API.

Fixes: b4fec647 ("ARM: dts: Add camera device nodes for Exynos4412 TRATS2 board")
Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20220913164104.203957-1-dmitry.torokhov@gmail.com
Link: https://lore.kernel.org/r/20220926104354.118578-2-krzysztof.kozlowski@linaro.org'
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Merge tag 'aspeed-6.1-devicetree' of git://git.kernel.org/pub/scm/linux/kernel/git/joel/bmc into arm/dt

ASPEED device tree updates for 6.1

 - New machines

  * AMD's DaytonaX AST2600 BMC, for the amd64 server
  * Ampre's Mt. Mitchell AST2600 BMC, for the AmpereOne arm64 server

 - Fixes and updates for bletchley, mtjade, yosemitev2 and the ast2600-evb

* tag 'aspeed-6.1-devicetree' of git://git.kernel.org/pub/scm/linux/kernel/git/joel/bmc:
  ARM: dts: aspeed: ast2600-evb-a1: Add compatible
  ARM: dts: aspeed: ast2600evb: Fix compatible string
  ARM: dts: aspeed: ast2600-evb: Enable Quad SPI RX tranfers
  ARM: dts: aspeed-g6: Enable more UART controllers
  ARM: dts: aspeed: yosemitev2: Disable the EEPROM driver
  ARM: dts: aspeed: Add AMD DaytonaX BMC
  dt-bindings: arm: aspeed: document AMD DaytonaX
  ARM: dts: aspeed: Yosemite V2: Enable OCP debug card
  ARM: dts: aspeed: mtjade: Remove gpio-keys entries
  ARM: dts: aspeed: Add device tree for Ampere's Mt. Mitchell BMC
  dt-bindings: arm: aspeed: document Ampere Mt.Mitchell BMC compatibles
  ARM: dts: aspeed: bletchley: Remove hdc1080 node
  ARM: dts: aspeed: bletchley: Add USB debug card IPMB node
  ARM: dts: aspeed: ast2600-evb: Update I2C devices

Link: https://lore.kernel.org/r/CACPK8Xepnci+f+7Pi1jtXod8Jmt+OnJYfDRENjiP-xDBQwFCVg@mail.gmail.comSigned-off-by: Arnd Bergmann <arnd@arndb.de>

Merge tag 'v6.1-rockchip-dts64-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/dt

RK3399-Nanopi-R4S-enterprise as variant board, Gru-Scarlet SKU variants,
DSI support for rk356x, display-gamma-control for rk3399, display
output for quartz64-b and rk3566-roc-pc, hdmi supplies for rk3399-roc-pc,
some pinctrl improvements for the px30-evb and a number of changes to
bring rk3399 rock4 and rock-pi4 structure closer to names used in schematics.

* tag 'v6.1-rockchip-dts64-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  arm64: dts: rockchip: use pin constant for reset-gpios on px30-evb
  arm64: dts: rockchip: add pinctrl for mipi-pdn pin on px30-evb
  arm64: dts: rockchip: set max drive-strength for cif_clkout_m0 on px30-evb
  arm64: dts: rockchip: add avdd-0v9-supply and avdd-1v8-supply on rk3399 rock 4c and pi4
  arm64: dts: rockchip: sort nodes/properties on rk3399-rock-4
  arm64: dts: rockchip: fix regulator name on rk3399-rock-4
  arm64: dts: rockchip: sort nodes/properties on rk3399-rock-4c-plus
  arm64: dts: rockchip: fix regulator structure on rk3399-rock-4c-plus
  arm64: dts: rockchip: connect vcca_1v8 to APIO5_VDD on rk3399-rock-4c-plus
  arm64: dts: rockchip: Add DSI and DSI-DPHY nodes to rk356x
  arm64: dts: rockchip: Enable HDMI and GPU on quartz64-b
  arm64: dts: rockchip: Add RK3399 NanoPi R4S Enterprise Edition
  dt-bindings: Add doc for FriendlyARM NanoPi R4S Enterprise Edition
  arm64: dts: rockchip: add i2s0 I2S/PDM/TDM 8ch controller to px30
  arm64: dts: rockchip: Add HDMI supplies on rk3399-roc-pc
  arm64: dts: rockchip: Support gru-scarlet sku{2,4} variants
  dt-bindings: arm: rockchip: Add gru-scarlet sku{2,4} variants
  arm64: dts: rockchip: enable gamma control on RK3399
  arm64: dts: rockchip: Enable video output on rk3566-roc-pc

Link: https://lore.kernel.org/r/38114097.10thIPus4b@philSigned-off-by: Arnd Bergmann <arnd@arndb.de>

The AST2600 EVB A1 is an AST2600 EVB.
Signed-off-by: Joel Stanley <joel@jms.id.au>

The AST2600 EVB is not an A1.
Signed-off-by: Joel Stanley <joel@jms.id.au>

Now that the pinctrl definitions of the ast2600 SoC have been fixed,
see commit 925fbe1f ("dt-bindings: pinctrl: aspeed-g6: add FWQSPI
function/group"), it is safe to activate QSPI on the ast2600 evb.

Cc: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Tested-by: Jae Hyun Yoo <quic_jaehyoo@quicinc.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Link: https://lore.kernel.org/r/20220603073705.1624351-1-clg@kaod.orgSigned-off-by: Joel Stanley <joel@jms.id.au>

Setup the configuration of UART6, UART7, UART8, and UART9 in
aspeed-g6.dtsi.
Signed-off-by: Ken Chen <j220584470k@gmail.com>
Link: https://lore.kernel.org/r/20220805090957.470434-1-j220584470k@gmail.comSigned-off-by: Joel Stanley <joel@jms.id.au>

Removed NIC EEPROM driver IPMB-12 channel and enabled it as
generic i2c EEPROM.
Signed-off-by: Karthikeyan Pasupathi <pkarthikeyan1509@gmail.com>
Link: https://lore.kernel.org/r/20220914115307.GA339@hcl-ThinkPad-T495Signed-off-by: Joel Stanley <joel@jms.id.au>

Add initial version of device tree for the BMC in the AMD DaytonaX
platform.

AMD DaytonaX platform is a customer reference board (CRB) with an
Aspeed ast2500 BMC manufactured by AMD.
Signed-off-by: Konstantin Aladyshev <aladyshev22@gmail.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20220921210950.10568-3-aladyshev22@gmail.comSigned-off-by: Joel Stanley <joel@jms.id.au>

Document AMD DaytonaX board compatible.
Signed-off-by: Konstantin Aladyshev <aladyshev22@gmail.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20220921210950.10568-2-aladyshev22@gmail.comSigned-off-by: Joel Stanley <joel@jms.id.au>

Added IPMB-13 channel for Debug Card communication which improves the
readability of the machine and makes it easier to debug the server and
it will display some pieces of information about the server like "system
info", "Critical sensors" and "critical sel".
Signed-off-by: Karthikeyan Pasupathi <pkarthikeyan1509@gmail.com>
Reviewed-by: Patrick Williams <patrick@stwcx.xyz>
Link: https://lore.kernel.org/r/20220926124313.GA8400@hcl-ThinkPad-T495Signed-off-by: Joel Stanley <joel@jms.id.au>

Remove the gpio-keys entries from the Ampere's Mt. Jade BMC device
tree. The user space applications are going to change from using
libevdev to libgpiod.
Signed-off-by: Quan Nguyen <quan@os.amperecomputing.com>
Link: https://lore.kernel.org/r/20220915080828.2894070-1-quan@os.amperecomputing.comSigned-off-by: Joel Stanley <joel@jms.id.au>

The Mt. Mitchell BMC is an ASPEED AST2600-based BMC for the Mt. Mitchell
hardware reference platform with AmpereOne(TM) processor.
Signed-off-by: Quan Nguyen <quan@os.amperecomputing.com>
Signed-off-by: Phong Vo <phong@os.amperecomputing.com>
Signed-off-by: Thang Q. Nguyen <thang@os.amperecomputing.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Link: https://lore.kernel.org/r/20220817071539.176110-3-quan@os.amperecomputing.comSigned-off-by: Joel Stanley <joel@jms.id.au>

Document Ampere Mt.Mitchell BMC board compatible.
Signed-off-by: Quan Nguyen <quan@os.amperecomputing.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20220817071539.176110-2-quan@os.amperecomputing.comSigned-off-by: Joel Stanley <joel@jms.id.au>

Merge tag 'mvebu-dt-6.1-1' of git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu into arm/dt

mvebu dt for 6.1 (part 1)

Add definitions for PCIe legacy INTx interrupts for dts using
pci-mvebu.c controller driver.

Add gpio-ranges for pin muxing for Armada 38x

Add audio support for Armada 38x

Turris-omnia (Armada 385 based) fix a pin name

lsxl (kirkwood based)
 - Fix fix serial line
 - Remove first ethernet port

* tag 'mvebu-dt-6.1-1' of git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu: (22 commits)
  ARM: dts: turris-omnia: Add label for wan port
  ARM: dts: turris-omnia: Define S/PDIF audio card
  ARM: mvebu: Add spdif-pins mpp pins for Armada 38x
  ARM: mvebu: add audio support to Armada 385 DB
  ARM: mvebu: add audio I2S controller to Armada 38x Device Tree
  ARM: dts: armada-38x: Add gpio-ranges for pin muxing
  ARM: dts: dove: Add definitions for PCIe error interrupts
  ARM: dts: kirkwood: Add definitions for PCIe error interrupts
  ARM: dts: armada-39x.dtsi: Add definitions for PCIe legacy INTx interrupts
  ARM: dts: armada-380.dtsi: Add definitions for PCIe legacy INTx interrupts
  ARM: dts: armada-375.dtsi: Add definitions for PCIe legacy INTx interrupts
  ARM: dts: armada-xp-mv78460.dtsi: Add definitions for PCIe legacy INTx interrupts
  ARM: dts: armada-xp-mv78260.dtsi: Add definitions for PCIe legacy INTx interrupts
  ARM: dts: armada-xp-mv78230.dtsi: Add definitions for PCIe legacy INTx interrupts
  ARM: dts: armada-xp-98dx3236.dtsi: Add definitions for PCIe legacy INTx interrupts
  ARM: dts: armada-370.dtsi: Add definitions for PCIe legacy INTx interrupts
  ARM: dts: dove: Add definitions for PCIe legacy INTx interrupts
  ARM: dts: kirkwood: Add definitions for PCIe legacy INTx interrupts
  ARM: dts: kirkwood: lsxl: remove first ethernet port
  ARM: dts: kirkwood: lsxl: fix serial line
  ...

Link: https://lore.kernel.org/r/87edw2xfle.fsf@BL-laptopSigned-off-by: Arnd Bergmann <arnd@arndb.de>