1. 01 Jun, 2020 5 commits
    • Stephen Boyd's avatar
      Merge branches 'clk-vc5', 'clk-hsdk', 'clk-mediatek' and 'clk-baikal' into clk-next · 166e4b48
      Stephen Boyd authored
       - Support IDT VersaClock 5P49V5925
       - Bunch of updates for HSDK clock generation unit (CGU) driver
       - New clk driver for Baikal-T1 SoCs
      
      * clk-vc5:
        dt: Add bindings for IDT VersaClock 5P49V5925
        clk: vc5: Add support for IDT VersaClock 5P49V6965
      
      * clk-hsdk:
        CLK: HSDK: CGU: add support for 148.5MHz clock
        CLK: HSDK: CGU: support PLL bypassing
        CLK: HSDK: CGU: check if PLL is bypassed first
      
      * clk-mediatek:
        clk: mediatek: assign the initial value to clk_init_data of mtk_mux
        clk: mediatek: Add MT6765 clock support
        clk: mediatek: add mt6765 clock IDs
        dt-bindings: clock: mediatek: document clk bindings vcodecsys for Mediatek MT6765 SoC
        dt-bindings: clock: mediatek: document clk bindings mipi0a for Mediatek MT6765 SoC
        dt-bindings: clock: mediatek: document clk bindings for Mediatek MT6765 SoC
      
      * clk-baikal:
        clk: Add Baikal-T1 CCU Dividers driver
        clk: Add Baikal-T1 CCU PLLs driver
        dt-bindings: clk: Add Baikal-T1 CCU Dividers binding
        dt-bindings: clk: Add Baikal-T1 CCU PLLs binding
      166e4b48
    • Stephen Boyd's avatar
      Merge branches 'clk-mmp', 'clk-intel', 'clk-ingenic', 'clk-qcom' and 'clk-silabs' into clk-next · 5debcd01
      Stephen Boyd authored
       - Start making audio and GPU clks work on Marvell MMP2/MMP3 SoCs
       - Add support for X1830 and X1000 Ingenic SoC clk controllers
       - Add support for Qualcomm's MSM8939 Generic Clock Controller
       - Add some GPU, NPU, and UFS clks to Qualcomm SM8150 driver
       - Enable supply regulators for GPU gdscs on Qualcomm SoCs
       - Add support for Si5342, Si5344 and Si5345 chips
      
      * clk-mmp:
        clk: mmp2: Add audio clock controller driver
        dt-bindings: clock: Add Marvell MMP Audio Clock Controller binding
        clk: mmp2: Add support for power islands
        dt-bindings: marvell,mmp2: Add ids for the power domains
        dt-bindings: clock: Make marvell,mmp2-clock a power controller
        clk: mmp2: Add the audio clock
        clk: mmp2: Add the I2S clocks
        clk: mmp2: Rename mmp2_pll_init() to mmp2_main_clk_init()
        clk: mmp2: Move thermal register defines up a bit
        dt-bindings: marvell,mmp2: Add clock id for the Audio clock
        dt-bindings: marvell,mmp2: Add clock id for the I2S clocks
        clk: mmp: frac: Allow setting bits other than the numerator/denominator
        clk: mmp: frac: Do not lose last 4 digits of precision
      
      * clk-intel:
        clk: intel: remove redundant initialization of variable rate64
        clk: intel: Add CGU clock driver for a new SoC
        dt-bindings: clk: intel: Add bindings document & header file for CGU
      
      * clk-ingenic:
        clk: ingenic: Mark ingenic_tcu_of_match as __maybe_unused
        clk: X1000: Add FIXDIV for SSI clock of X1000.
        dt-bindings: clock: Add and reorder ABI for X1000.
        clk: Ingenic: Add CGU driver for X1830.
        dt-bindings: clock: Add X1830 clock bindings.
        clk: Ingenic: Adjust cgu code to make it compatible with X1830.
        clk: Ingenic: Remove unnecessary spinlock when reading registers.
      
      * clk-qcom:
        clk: qcom: Add missing msm8998 ufs_unipro_core_clk_src
        dt-bindings: clock: Add YAML schemas for QCOM A53 PLL
        clk: qcom: gcc-msm8939: Add MSM8939 Generic Clock Controller
        clk: qcom: gcc: Add support for Secure control source clock
        dt-bindings: clock: Add gcc_sec_ctrl_clk_src clock ID
        clk: qcom: gcc: Add support for a new frequency for SC7180
        clk: qcom: Add DT bindings for MSM8939 GCC
        clk: qcom: gcc: Add missing UFS clocks for SM8150
        clk: qcom: gcc: Add GPU and NPU clocks for SM8150
        clk: qcom: mmcc-msm8996: Properly describe GPU_GX gdsc
        clk: qcom: gdsc: Handle GDSC regulator supplies
        clk: qcom: msm8916: Fix the address location of pll->config_reg
      
      * clk-silabs:
        clk: clk-si5341: Add support for the Si5345 series
      5debcd01
    • Stephen Boyd's avatar
      Merge branches 'clk-unisoc', 'clk-trivial', 'clk-bcm', 'clk-st' and 'clk-ast2600' into clk-next · b6f3162d
      Stephen Boyd authored
      * clk-unisoc:
        clk: sprd: add mipi_csi_xx gate clocks
        clk: sprd: add dt-bindings include for mipi_csi_xx clocks
        dt-bindings: clk: sprd: add mipi_csi_xx clocks for SC9863A
        clk: sprd: check its parent status before reading gate clock
        clk: sprd: return correct type of value for _sprd_pll_recalc_rate
        clk: sprd: mark the local clock symbols static
      
      * clk-trivial:
        clk: versatile: remove redundant assignment to pointer clk
        clk: clk-xgene: Fix a typo in Kconfig
        clk: Remove unused inline function clk_debug_reparent
      
      * clk-bcm:
        clk: bcm2835: Constify struct debugfs_reg32
        clk: bcm2835: Remove casting to bcm2835_clk_register
        clk: bcm2835: Fix return type of bcm2835_register_gate
      
      * clk-st:
        clk: clk-flexgen: fix clock-critical handling
      
      * clk-ast2600:
        clk: ast2600: Fix AHB clock divider for A1
      b6f3162d
    • Stephen Boyd's avatar
      Merge branches 'clk-tegra', 'clk-imx', 'clk-zynq', 'clk-socfpga', 'clk-at91'... · 8c88e568
      Stephen Boyd authored
      Merge branches 'clk-tegra', 'clk-imx', 'clk-zynq', 'clk-socfpga', 'clk-at91' and 'clk-ti' into clk-next
      
       - Support custom flags in Xilinx zynq firmware
       - Various small fixes to the Xilinx clk driver
       - Support for Intel Agilex clks
      
      * clk-tegra:
        clk: tegra: Add Tegra210 CSI TPG clock gate
        clk: tegra30: Use custom CCLK implementation
        clk: tegra20: Use custom CCLK implementation
        clk: tegra: cclk: Add helpers for handling PLLX rate changes
        clk: tegra: pll: Add pre/post rate-change hooks
        clk: tegra: Add custom CCLK implementation
        clk: tegra: Remove the old emc_mux clock for Tegra210
        clk: tegra: Implement Tegra210 EMC clock
        clk: tegra: Export functions for EMC clock scaling
        clk: tegra: Add PLLP_UD and PLLMB_UD for Tegra210
        clk: tegra: Rename Tegra124 EMC clock source file
        dt-bindings: clock: tegra: Add clock ID for CSI TPG clock
      
      * clk-imx:
        clk: imx: use imx8m_clk_hw_composite_bus for i.MX8M bus clk slice
        clk: imx: add imx8m_clk_hw_composite_bus
        clk: imx: add mux ops for i.MX8M composite clk
        clk: imx8m: migrate A53 clk root to use composite core
        clk: imx8mp: use imx8m_clk_hw_composite_core to simplify code
        clk: imx8mp: Define gates for pll1/2 fixed dividers
        clk: imx: imx8mp: fix pll mux bit
        clk: imx8m: drop clk_hw_set_parent for A53
        dt-bindings: clocks: imx8mp: Add ids for audiomix clocks
        clk: imx: Add helpers for passing the device as argument
        clk: imx: pll14xx: Add the device as argument when registering
        clk: imx: gate2: Allow single bit gating clock
        clk: imx: clk-pllv3: Use readl_relaxed_poll_timeout() for PLL lock wait
        clk: imx: clk-sscg-pll: Remove unnecessary blank lines
        clk: imx: drop the dependency on ARM64 for i.MX8M
        clk: imx7ulp: make it easy to change ARM core clk
        clk: imx: imx6ul: change flexcan clock to support CiA bitrates
      
      * clk-zynq:
        clk: zynqmp: Make zynqmp_clk_get_max_divisor static
        clk: zynqmp: Update fraction clock check from custom type flags
        clk: zynqmp: Add support for custom type flags
        clk: zynqmp: fix memory leak in zynqmp_register_clocks
        clk: zynqmp: Fix invalid clock name queries
        clk: zynqmp: Fix divider2 calculation
        clk: zynqmp: Limit bestdiv with maxdiv
      
      * clk-socfpga:
        clk: socfpga: agilex: add clock driver for the Agilex platform
        dt-bindings: documentation: add clock bindings information for Agilex
        clk: socfpga: add const to _ops data structures
        clk: socfpga: remove clk_ops enable/disable methods
        clk: socfpga: stratix10: use new parent data scheme
      
      * clk-at91:
        clk: at91: allow setting all PMC clock parents via DT
        clk: at91: allow setting PCKx parent via DT
        clk: at91: optimize pmc data allocation
        clk: at91: pmc: decrement node's refcount
        clk: at91: pmc: do not continue if compatible not located
        clk: at91: Add peripheral clock for PTC
      
      * clk-ti:
        clk: ti: dra7: remove two unused symbols
        clk: ti: dra7xx: fix RNG clock parent
        clk: ti: dra7xx: mark MCAN clock as DRA76x only
        clk: ti: dra7xx: fix gpu clkctrl parent
        clk: ti: omap5: Add proper parent clocks for l4-secure clocks
        clk: ti: omap4: Add proper parent clocks for l4-secure clocks
        clk: ti: composite: fix memory leak
      8c88e568
    • Stephen Boyd's avatar
      Merge branches 'clk-selectable', 'clk-amlogic', 'clk-renesas', 'clk-samsung'... · 3a57530b
      Stephen Boyd authored
      Merge branches 'clk-selectable', 'clk-amlogic', 'clk-renesas', 'clk-samsung' and 'clk-allwinner' into clk-next
      
       - Allow the COMMON_CLK config to be selectable
      
      * clk-selectable:
        clk: Move HAVE_CLK config out of architecture layer
        MIPS: Loongson64: Drop asm/clock.h include
        ARM: mmp: Remove legacy clk code
        clk: Allow the common clk framework to be selectable
        mmc: meson-mx-sdio: Depend on OF_ADDRESS and not just OF
        MIPS: Remove redundant CLKDEV_LOOKUP selects
        h8300: Remove redundant CLKDEV_LOOKUP selects
        arm64: tegra: Remove redundant CLKDEV_LOOKUP selects
        ARM: Remove redundant CLKDEV_LOOKUP selects
        ARM: Remove redundant COMMON_CLK selects
      
      * clk-amlogic:
        clk: meson: meson8b: Don't rely on u-boot to init all GP_PLL registers
        clk: meson: meson8b: Make the CCF use the glitch-free VPU mux
        clk: meson: meson8b: Fix the vclk_div{1, 2, 4, 6, 12}_en gate bits
        clk: meson: meson8b: Fix the polarity of the RESET_N lines
        clk: meson: meson8b: Fix the first parent of vid_pll_in_sel
        clk: meson: g12a: Prepare the GPU clock tree to change at runtime
        clk: meson: gxbb: Prepare the GPU clock tree to change at runtime
        clk: meson: meson8b: make the hdmi_sys clock tree mutable
        clk: meson8b: export the HDMI system clock
      
      * clk-renesas:
        dt-bindings: clock: renesas: mstp: Convert to json-schema
        dt-bindings: clock: renesas: div6: Convert to json-schema
        clk: renesas: cpg-mssr: Fix STBCR suspend/resume handling
        clk: renesas: rcar-gen2: Remove superfluous CLK_RENESAS_DIV6 selects
        clk: renesas: cpg-mssr: Add R8A7742 support
        dt-bindings: clock: renesas: cpg-mssr: Document r8a7742 binding
        clk: renesas: Add r8a7742 CPG Core Clock Definitions
        dt-bindings: power: rcar-sysc: Add r8a7742 power domain index macros
        MAINTAINERS: Add DT Bindings for Renesas Clock Generators
        clk: renesas: r9a06g032: Fix some typo in comments
        dt-bindings: clock: renesas: rcar-usb2-clock-sel: Add r8a77961 support
      
      * clk-samsung:
        clk: samsung: exynos5433: Add IGNORE_UNUSED flag to sclk_i2s1
        ARM/SAMSUNG EXYNOS ARM ARCHITECTURES: Use fallthrough;
        clk: samsung: Fix CLK_SMMU_FIMCL3 clock name on Exynos542x
        clk: samsung: Mark top ISP and CAM clocks on Exynos542x as critical
      
      * clk-allwinner:
        clk: sunxi: Fix incorrect usage of round_down()
      3a57530b
  2. 30 May, 2020 6 commits
    • Adam Ford's avatar
      dt: Add bindings for IDT VersaClock 5P49V5925 · d63ed4ff
      Adam Ford authored
      IDT VersaClock 5 5P49V6965 has 5 clock outputs, 4 fractional dividers.
      Signed-off-by: default avatarAdam Ford <aford173@gmail.com>
      Link: https://lkml.kernel.org/r/20200404161537.2312297-2-aford173@gmail.comAcked-by: default avatarRob Herring <robh@kernel.org>
      Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
      d63ed4ff
    • Adam Ford's avatar
      clk: vc5: Add support for IDT VersaClock 5P49V6965 · 2bda748e
      Adam Ford authored
      Update IDT VersaClock 5 driver to support 5P49V6965.
      Signed-off-by: default avatarAdam Ford <aford173@gmail.com>
      Link: https://lore.kernel.org/r/20200404161537.2312297-1-aford173@gmail.comSigned-off-by: default avatarStephen Boyd <sboyd@kernel.org>
      2bda748e
    • Serge Semin's avatar
      clk: Add Baikal-T1 CCU Dividers driver · 353afa3a
      Serge Semin authored
      Nearly each Baikal-T1 IP-core is supposed to have a clock source
      of particular frequency. But since there are greater than five
      IP-blocks embedded into the SoC, the CCU PLLs can't fulfill all the
      needs. Baikal-T1 CCU provides a set of fixed and configurable clock
      dividers in order to generate a necessary signal for each chip
      sub-block.
      
      This driver creates the of-based hardware clocks for each divider
      available in Baikal-T1 CCU. The same way as for PLLs we split the
      functionality up into the clocks operations (gate, ungate, set rate,
      etc) and hardware clocks declaration/registration procedures.
      
      In accordance with the CCU documentation all its dividers are distributed
      into two CCU sub-blocks: AXI-bus and system devices reference clocks.
      The former sub-block is used to supply the clocks for AXI-bus interfaces
      (AXI clock domains) and the later one provides the SoC IP-cores reference
      clocks. Each sub-block is represented by a dedicated DT node, so they
      have different compatible strings to distinguish one from another.
      
      For some reason CCU provides the dividers of different types. Some
      dividers can be gateable some can't, some are fixed while the others
      are variable, some have special divider' limitations, some've got a
      non-standard register layout and so on. In order to cover all of these
      cases the hardware clocks driver is designed with an info-descriptor
      pattern. So there are special static descriptors declared for the
      dividers of each type with additional flags describing the block
      peculiarity. These descriptors are then used to create hardware clocks
      with proper operations.
      
      Some CCU dividers provide a way to reset a domain they generate
      a clock for. So the CCU AXI-bus and CCU system devices clock
      drivers also perform the reset controller registration.
      Signed-off-by: default avatarSerge Semin <Sergey.Semin@baikalelectronics.ru>
      Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
      Cc: Arnd Bergmann <arnd@arndb.de>
      Cc: Rob Herring <robh+dt@kernel.org>
      Cc: linux-mips@vger.kernel.org
      Cc: devicetree@vger.kernel.org
      Link: https://lore.kernel.org/r/20200526222056.18072-5-Sergey.Semin@baikalelectronics.ru
      [sboyd@kernel.org: Drop return from void function, silence sparse
      warnings about initializing structs with NULL vs. integer]
      Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
      353afa3a
    • Serge Semin's avatar
      clk: Add Baikal-T1 CCU PLLs driver · b7d950b9
      Serge Semin authored
      Baikal-T1 is supposed to be supplied with a high-frequency external
      oscillator. But in order to create signals suitable for each IP-block
      embedded into the SoC the oscillator output is primarily connected to
      a set of CCU PLLs. There are five of them to create clocks for the MIPS
      P5600 cores, an embedded DDR controller, SATA, Ethernet and PCIe domains.
      The last three domains though named by the biggest system interfaces in
      fact include nearly all of the rest SoC peripherals. Each of the PLLs is
      based on True Circuits TSMC CLN28HPM IP-core with an interface wrapper
      (so called safe PLL' clocks switcher) to simplify the PLL configuration
      procedure.
      
      This driver creates the of-based hardware clocks to use them then in
      the corresponding subsystems. In order to simplify the driver code we
      split the functionality up into the PLLs clocks operations and hardware
      clocks declaration/registration procedures.
      
      Even though the PLLs are based on the same IP-core, they may have some
      differences. In particular, some CCU PLLs support the output clock change
      without gating them (like CPU or PCIe PLLs), while the others don't, some
      CCU PLLs are critical and aren't supposed to be gated. In order to cover
      all of these cases the hardware clocks driver is designed with an
      info-descriptor pattern. So there are special static descriptors declared
      for each PLL, which is then used to create a hardware clock with proper
      operations. Additionally debugfs-files are provided for each PLL' field
      to make sure the implemented rate-PLLs-dividers calculation algorithm is
      correct.
      Signed-off-by: default avatarSerge Semin <Sergey.Semin@baikalelectronics.ru>
      Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
      Cc: Arnd Bergmann <arnd@arndb.de>
      Cc: Rob Herring <robh+dt@kernel.org>
      Cc: linux-mips@vger.kernel.org
      Cc: devicetree@vger.kernel.org
      Link: https://lore.kernel.org/r/20200526222056.18072-4-Sergey.Semin@baikalelectronics.ru
      [sboyd@kernel.org: Silence sparse warning about initializing structs
      with NULL vs. integer]
      Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
      b7d950b9
    • Serge Semin's avatar
      dt-bindings: clk: Add Baikal-T1 CCU Dividers binding · 11ea09b9
      Serge Semin authored
      After being gained by the CCU PLLs the signals must be transformed to
      be suitable for the clock-consumers. This is done by a set of dividers
      embedded into the CCU. A first block of dividers is used to create
      reference clocks for AXI-bus of high-speed peripheral IP-cores of the
      chip. The second block dividers alter the PLLs output signals to be then
      consumed by SoC peripheral devices. Both block DT nodes are ordinary
      clock-providers with standard set of properties supported. But in addition
      to that each clock provider can be used to reset the corresponding clock
      domain. This makes the AXI-bus and System Devices CCU DT nodes to be also
      reset-providers.
      Signed-off-by: default avatarSerge Semin <Sergey.Semin@baikalelectronics.ru>
      Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
      Cc: Arnd Bergmann <arnd@arndb.de>
      Cc: linux-mips@vger.kernel.org
      Link: https://lore.kernel.org/r/20200526222056.18072-3-Sergey.Semin@baikalelectronics.ruReviewed-by: default avatarRob Herring <robh@kernel.org>
      Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
      11ea09b9
    • Serge Semin's avatar
      dt-bindings: clk: Add Baikal-T1 CCU PLLs binding · aec6adc5
      Serge Semin authored
      Baikal-T1 Clocks Control Unit is responsible for transformation of a
      signal coming from an external oscillator into clocks of various
      frequencies to propagate them then to the corresponding clocks
      consumers (either individual IP-blocks or clock domains). In order
      to create a set of high-frequency clocks the external signal is
      firstly handled by the embedded into CCU PLLs. So the corresponding
      dts-node is just a normal clock-provider node with standard set of
      properties. Note as being part of the Baikal-T1 System Controller its
      DT node is supposed to be a child the system controller node.
      Signed-off-by: default avatarSerge Semin <Sergey.Semin@baikalelectronics.ru>
      Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
      Cc: Arnd Bergmann <arnd@arndb.de>
      Cc: linux-mips@vger.kernel.org
      Link: https://lore.kernel.org/r/20200526222056.18072-2-Sergey.Semin@baikalelectronics.ruReviewed-by: default avatarRob Herring <robh@kernel.org>
      Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
      aec6adc5
  3. 29 May, 2020 10 commits
  4. 28 May, 2020 19 commits