From Shawn Guo:
imx6q cpuidle support for 3.9

 - It's based on imx-cleanup-3.9 to avoid conflicts.

* tag 'imx6q-cpudile-3.9' of git://git.linaro.org/people/shawnguo/linux-2.6:
  ARM: imx6q: support WAIT mode using cpuidle
  ARM: imx: move imx6q_cpuidle_driver into a separate file
  ARM: imx: mask gpc interrupts initially
  ARM: imx: return zero in case next event gets a large increment
  ARM: imx: Remove mx508 support
  ARM: imx: Remove mach-mx51_3ds board
  ARM: imx: use debug_ll_io_init() for imx6q
  ARM: imx: remove unused imx6q_clock_map_io()
  ARM: mach-imx: Kconfig: Do not select Babbage for MACH_IMX51_DT
Signed-off-by: Olof Johansson <olof@lixom.net>

Still, two delete/change conflicts caused by imx/cleanup:

	arch/arm/mach-imx/mach-mx50_rdp.c
	arch/arm/mach-imx/mach-mx51_3ds.c

Fix the issue:
tree:   git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git next/soc
head:   6ed05a2a
commit: af70fdc9 [4/8] Merge branch 'marco-timer-cleanup-rebase' of
git://gitorious.org/sirfprima2-kernel/sirfprima2-kernel into next/soc
config: make ARCH=arm prima2_defconfig

All error/warnings:

>> arch/arm/mach-prima2/platsmp.c:20:30: fatal error: asm/hardware/gic.h: No such file or directory
   compilation terminated.
--
>> arch/arm/mach-prima2/common.c:15:30: fatal error: asm/hardware/gic.h: No such file or directory
   compilation terminated.
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Cc: Xie ChanglongX <changlongx.xie@intel.com>
Signed-off-by: Olof Johansson <olof@lixom.net>

Merge tag 'renesas-soc2-for-v3.9' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc

From Simon Horman:
Second round of Renesas ARM-based SoC changes for v3.9

* Changes to allow unplugging of CPU0 by Ulrich Hecht.

* Changes to add reg and device_type properties to cpus
  device trees entries by Simon Horman.

* tag 'renesas-soc2-for-v3.9' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
  ARM: mach-shmobile: sh73a0: allow unplugging of CPU0
  ARM: mach-shmobile: add shmobile_cpu_disable_any()
  ARM: mach-shmobile: emev2:  Add reg and device_type properties to cpus
  ARM: mach-shmobile: sh73a0:  Add reg and device_type properties to cpus
Signed-off-by: Olof Johansson <olof@lixom.net>

Add WAIT mode (ARM core clock gating) support to imx6q cpuidle driver.
As WAIT mode is broken on imx6q TO 1.0 and 1.1, it only enables the
support for revision 1.2 with chicken bit set.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

Move imx6q_cpuidle_driver into a separate file as more codes will
be added when WAIT mode gets implemented as cpuidle.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

Mask gpc interrupts initially to avoid suspicious interrupts.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

The return of v2_set_next_event() will lead to an infinite loop in
tick_handle_oneshot_broadcast() - "goto again;" with imx6q WAIT mode
(to be enabled).  This happens because when global event did not expire
any CPU local events, the broadcast device will be rearmed to a CPU
local next_event, which could be far away from now and result in a
max_delta_tick programming in set_next_event().

Fix the problem by detecting those next events with increments larger
than 0x7fffffff, and simply return zero in that case.

It leaves mx1_2_set_next_event() unchanged since only v2_set_next_event()
will be running with imx6q WAIT mode support.

Thanks Russell King for helping understand the problem.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

sh73a0 deals fine with disabling any core, so we should permit it.
Signed-off-by: Ulrich Hecht <ulrich.hecht@gmail.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

Method to disable any core to be used on platforms where CPU0 does not
need special treatment.
Signed-off-by: Ulrich Hecht <ulrich.hecht@gmail.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

Merge tag 'bcm2835-for-3.9-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-rpi into next/soc

From Stephen Warren:
ARM: bcm2835: SoC driver updates

The bcm2835 clock driver is enhanced to allow fixed clocks to be probed
from device tree.

A system power-off implementation is added.

This branch is based on v3.8-rc3.

* tag 'bcm2835-for-3.9-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-rpi:
  ARM: bcm2835: add a pm_power_off implementation
  clk: bcm2835: probe for fixed-clock in device tree
Signed-off-by: Olof Johansson <olof@lixom.net>

From Sekhar Nori:
DaVinci SoC changes for v3.9

This pull request:

1) Fixes a bug with the way SPI devices were registered on DA850
2) Adds support for DSP clock and resetting the DSP on DA850
3) Fixes checkpatch issue with some existing files.

* tag 'davinci-for-v3.9/soc' of git://gitorious.org/linux-davinci/linux-davinci:
  ARM: davinci: da850: add dsp clock definition
  ARM: davinci: psc: introduce reset API
  ARM: davinci: psc.c: change pr_warning() to pr_warn()
  ARM: davinci: devices-da8xx.c: change pr_warning() to pr_warn()
  ARM: davinci: da8xx_register_spi() should not register SPI board info
Signed-off-by: Olof Johansson <olof@lixom.net>

From Simon Horman, a series of SoC updates for shmobile.

* 'soc' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
  ARM: shmobile: r8a7779: scif .irqs used SCIx_IRQ_MUXED()
  ARM: mach-shmobile: sh73a0: Initialise MMCIF using DT
  ARM: mach-shmobile: sh73a0: Minimal setup using DT
  ARM: mach-shmobile: sh73a0: Allow initialisation of GIC by DT
  ARM: SH-Mobile: sh73a0: Add CPU Hotplug
  ARM: SH-Mobile: sh73a0: Secondary CPUs handle own SCU flags
  ARM: shmobile: r8a7740: Add CPU sleep suspend
  ARM: shmobile: sh73a0: Add CPU sleep suspend
  ARM: shmobile: add function declarations for sh7372 DT helper functions
  ARM: sh7372: fix cache clean / invalidate order
  ARM: sh7372: add clock lookup entries for DT-based devices
  ARM: mach-shmobile: sh73a0 external IRQ wake update
  ARM: shmobile: sh73a0: fixup div4_clks bitmap
  ARM: shmobile: r8a7740: add TMU timer support
  ARM: shmobile: Remove duplicate inclusion of dma-mapping.h in setup-r8a7740.c
Signed-off-by: Olof Johansson <olof@lixom.net>

Fix trivial conflict in board_bcm due to Simon resolving the same conflict
with one less line of whitespace. Keeping end result common with what
we already have in arm-soc.

Conflicts:
	arch/arm/mach-bcm/board_bcm.c

Only mx508 based board is mach-mx50_rdp and it has been marked as BROKEN
for several releases.

mx508 currently lacks clock support.

In case someone needs to add mx508 support back, then the recommended approach
is to use device tree.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

mach-mx51_3ds only supports old silicon version of MX51 and was replaced
with mx51 babbage, which is the official MX51 development board.

No need to maintain it anymore.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

Use debug_ll_io_init() to map low level debug port for imx6q, so that
arch/arm/mach-imx/lluart.c can be removed.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

imx6q_clock_map_io() becomes an empty function since imx6q clock driver
is moved to common clock framework.  It's used nowhere now.  Remove it.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

Cc: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

Cc: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

From Sascha Hauer:
ARM i.MX SoC updates for next

Mostly clock related updates, most notably the conversion of
i.MX31 to a DT based lookup.

* tag 'imx-soc' of git://git.pengutronix.de/git/imx/linux-2.6:
  ARM: clk-imx35: Fix build warnings with W=1
  ARM: imx27: add a clock gate to activate SPLL clock
  ARM: mx31: Replace clk_register_clkdev with clock DT lookup
  ARM: clk-imx31: Add dummy clock
  ARM: Let CONFIG_MACH_IMX31_DT be built by default
Signed-off-by: Olof Johansson <olof@lixom.net>

Merge branch 'marco-timer-cleanup-rebase' of git://gitorious.org/sirfprima2-kernel/sirfprima2-kernel into next/soc

From Barry Song, this adds support for a new SoC from CSR; marco. It's
SMP, uses GIC instead of VIC and in general needs a bit of rework of
the platform code for setup, which this branch contains.

* 'marco-timer-cleanup-rebase' of git://gitorious.org/sirfprima2-kernel/sirfprima2-kernel:
  ARM: PRIMA2: provide two DEBUG_LL ports for prima2 and marco
  ARM: PRIMA2: add new SiRFmarco SMP SoC infrastructures
  ARM: PRIMA2: irq: make prima2 irq can work even we enable GIC for Marco
  ARM: PRIMA2: rtciobg: it is also compatible with marco
  ARM: PRIMA2: rstc: enable the support for Marco
  ARM: PRIMA2: mv timer to timer-prima2 as we will add timer-marco
  ARM: PRIMA2: initialize l2x0 according to mach from DT
  ARM: PRIMA2: enable AUTO_ZRELADDR for SIRF in Kconfig
  ARM: PRIMA2: add CSR SiRFmarco device tree .dts
Signed-off-by: Olof Johansson <olof@lixom.net>

Signed-off-by: Olof Johansson <olof@lixom.net>

Fix the following warnings when building with W=1 option:

arch/arm/mach-imx/clk-imx35.c: In function 'mx35_clocks_init':
arch/arm/mach-imx/clk-imx35.c:70:12: warning: old-style function definition [-Wold-style-definition]
arch/arm/mach-imx/clk-imx35.c:201:16: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

A clock gate is mandatory to activate SPLL clock needed, at least, for usb.
Signed-off-by: Gwenhael Goavec-Merou <gwenhael.goavec-merou@armadeus.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Similarly as it was done for mx6q, use a DT lookup in order to make maintainance
task for the clock devices easier.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Add dummy clock as it is required by some i.mx drivers.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Let CONFIG_MACH_IMX31_DT be built by default.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

This patch tidyup scif .irqs settings by using
SCIx_IRQ_MUXED() macro.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

This device also requires a voltage regulator which
should be defined in a board-specific maner. An example
dts snipped follows.

/ {
	fixedregulator1v8: fixedregulator@0 {
		compatible = "regulator-fixed";
		regulator-name = "fixed-1.8V";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
	};
};

&mmcif {
	vmmc-supply = <&fixedregulator1v8>;
	vqmmc-supply = <&fixedregulator1v8>;
};
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

Allow a minimal setup of the sh73a0 SoC using a flattened device tree.
In particular, Configure the i2c controllers using a flattened device tree.

SCI serial controller and CMT clock source, whose drivers do not yet
support configuration using a flattened device tree, are still configured
using C code in order to allow booting of a board with this SoC.

*** Please note that the clock initialisation scheme used in
    this patch does not currently work with SMP as there
    is a yet to be resolved lock-up in workqueue initialisation.

    CONFIG_SMP must be disabled when using this code. ***

Includes update from Thierry Reding to no longer use gic_handle_irq()

Cc: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

fix

This allows the GIC interrupt controller of the sh73a0 SoC to be
initialised using a flattened device tree blob.

It does not allow the INTC interrupt controller which is also present on
the sh73a0 SoC to be enabled via device tree.  Nor does it handle sharing
of interrupts between the GIC and INTC interrupt controllers.

This limits the usefulness of this code to applications which only wish to
access devices which use interrupts that can be handled by the GIC
interrupt controller. Other applications should, for now, continue using
non-device tree initialisation of the sh72a0 interrupt controllers.

Includes update to use irqchip_init() by Thierry Reding

Cc: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

Add the capability to add and remove CPUs on the fly.
The Cortex-A9 offers the possibility to take single cores out of the
MP Core. We add this capabilty taking care that caches are kept
coherent. For verifying the shutdown we rely on the internal SH73A0
Power Status Register PSTR.
Signed-off-by: Bastian Hecht <hechtb+renesas@gmail.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

When booting secondary CPUs we have used the main CPU to set up the
Snoop Control Unit flags of these CPUs. It is a cleaner approach
if every CPU takes care of its own flags. We avoid the need for
locking and the program logic is more concise. With this patch the file
headsmp-sh73a0.S is added that contains a startup vector for secondary CPUs
that sets up its own SCU flags.
Further in sh73a0_smp_prepare_cpus() we can rely on the generic ARM helper
scu_power_mode(). This is possible as we don't cross borders anymore (every
CPU handles its own flags) and need no locking. So we can throw out the
needless function modify_scu_cpu_psr().
Signed-off-by: Bastian Hecht <hechtb+renesas@gmail.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

Add the lighest possible sleep mode on Cortex-A9 cores: CPU sleep.
It is entered by a simple dsb and wfi instruction via cpu_do_idle(). As
just clocks are stopped there is no need to save or restore any state of
the system.
Signed-off-by: Bastian Hecht <hechtb+renesas@gmail.com>
Acked-by: Magnus Damm <damm@opensource.se>
[ horms@verge.net.au: Added missing includes ]
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

Add the lighest possible sleep mode on Cortex-A9 cores: CPU sleep. It is
entered by a simple dsb and wfi instruction via cpu_do_idle(). As just
clocks are stopped there is no need to save or restore any state of the
system.
Signed-off-by: Bastian Hecht <hechtb+renesas@gmail.com>
Acked-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

sh7372_add_early_devices_dt() and sh7372_add_standard_devices_dt() are
defined as global functions in arch/arm/mach-shmobile/setup-sh7372.c,
but their declarations are missing. Add them to common.h, where similar
functions for this and other SoC types are already declared.
Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Signed-off-by: Simon Horman <horms@verge.net.au>

According to the Cortex A8 TRM the L2 cache should be first cleaned and
then disabled. Fix the swapped order on sh7372.
Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

When booting with DT, devices are named differently. To get their clocks
additional entries have to be added to the lookup table.
Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Signed-off-by: Simon Horman <horms@verge.net.au>

Use sh73a0_set_wake() for external IRQ signals on sh73a0.

The sh73a0 IRQ hardware for external IRQ pins consists of
the INTCA interrupt controller and the GIC together doing
their best to limp along. These external IRQ pins are
treated as a special case where interrupts need to be
managed in both interrupt controllers in parallel.

The ->irq_set_wake() callback for the external IRQ pins
can be dealt with in the same way as INTCA-only without
involving the GIC. So this patch updates the external
IRQ pin code for sh73a0 to no longer involve the GIC.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

div4_clks's bitmap of sh73a0 was wrong.
This patch is based on v2.0 datasheet.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>