- 02 Aug, 2023 40 commits
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MD Danish Anwar authored
Add icssg_ethtool.c file. This file will be used for dumping statistics via ethtool for ICSSG ethernet driver. Reviewed-by:
Andrew Lunn <andrew@lunn.ch> Signed-off-by:
MD Danish Anwar <danishanwar@ti.com> Signed-off-by:
David S. Miller <davem@davemloft.net>
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MD Danish Anwar authored
Implement .ndo_get_stats64 to dump standard network interface statistics for ICSSG ethernet driver. Signed-off-by:
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MD Danish Anwar authored
Add icssg_stats.c to help dump, icssg related driver statistics. ICSSG has hardware registers for providing statistics like total rx bytes, total tx bytes, etc. These registers are of 32 bits and hence in case of 1G link, they overflows in around 32 seconds. The behaviour of these registers is such that they don't roll back to 0 after overflow but rather stay at UINT_MAX. These registers support a feature where the value written to them is subtracted from the register. This feature can be utilized to fix the overflowing of stats. This solution uses a Workqueues based solution where a function gets called before the registers overflow (every 25 seconds in 1G link, 25000 seconds in 100M link), this function saves the register values in local variables and writes the last read value to the register. So any update during the read will be taken care of. Signed-off-by:
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Roger Quadros authored
This is the Ethernet driver for TI AM654 Silicon rev. 2 with the ICSSG PRU Sub-system running dual-EMAC firmware. The Programmable Real-time Unit and Industrial Communication Subsystem Gigabit (PRU_ICSSG) is a low-latency microcontroller subsystem in the TI SoCs. This subsystem is provided for the use cases like implementation of custom peripheral interfaces, offloading of tasks from the other processor cores of the SoC, etc. Every ICSSG core has two Programmable Real-Time Unit(PRUs), two auxiliary Real-Time Transfer Unit (RT_PRUs), and two Transmit Real-Time Transfer Units (TX_PRUs). Each one of these runs its own firmware. Every ICSSG core has two MII ports connect to these PRUs and also a MDIO port. The cores can run different firmwares to support different protocols and features like switch-dev, timestamping, etc. It uses System DMA to transfer and receive packets and shared memory register emulation between the firmware and driver for control and configuration. This patch adds support for basic EMAC functionality with 1Gbps and 100Mbps link speed. 10M and half duplex mode are not supported currently as they require IEP, the support for which will be added later. Support for switch-dev, timestamp, etc. will be added later by subsequent patch series. Signed-off-by:
Roger Quadros <rogerq@ti.com> Signed-off-by:
Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by:
Grygorii Strashko <grygorii.strashko@ti.com> Reviewed-by:
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MD Danish Anwar authored
Add a YAML binding document for the ICSSG Programmable real time unit based Ethernet hardware. The ICSSG driver uses the PRU and PRUSS consumer APIs to interface the PRUs and load/run the firmware for supporting ethernet functionality. Reviewed-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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MD Danish Anwar authored
Add icssg_queue.c file. This file introduces macros and APIs related to ICSSG queues. These will be used by ICSSG Ethernet driver. Reviewed-by:
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MD Danish Anwar authored
Add icssg_config.h / .c and icssg_classifier.c files. These are firmware configuration and classification related files. These will be used by ICSSG ethernet driver. Reviewed-by:
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MD Danish Anwar authored
Add MII helper APIs and MACROs. These APIs and MACROs will be later used by ICSSG Ethernet driver. Also introduce icssg_prueth.h which has definition of prueth related structures. Reviewed-by:
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MD Danish Anwar authored
Add firmware interface related headers and macros for ICSSG Ethernet driver. These macros will be later used by the ICSSG ethernet driver. Reviewed-by:
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Ante Knezic authored
Fixes XAUI/RXAUI lane alignment errors. Issue causes dropped packets when trying to communicate over fiber via SERDES lanes of port 9 and 10. Errata document applies only to 88E6190X and 88E6390X devices. Requires poking in undocumented registers. Signed-off-by:
Ante Knezic <ante.knezic@helmholz.de> Reviewed-by:
Vladimir Oltean <olteanv@gmail.com> Signed-off-by:
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David S. Miller authored
Ratheesh Kannoth says: ==================== Packet classify by matching against SPI 1. net: flow_dissector: Add IPSEC dissector. Flow dissector patch reads IPSEC headers (ESP or AH) header from packet and retrieves the SPI header. 2. tc: flower: support for SPI. TC control path changes to pass SPI field from userspace to kernel. 3. tc: flower: Enable offload support IPSEC SPI field. Next patch enables the HW support for classify offload for ESP/AH. This patch enables the HW offload control. 4. octeontx2-pf: TC flower offload support for SPI field. HW offload support for classification in octeontx2 driver. ==================== Signed-off-by: -
Ratheesh Kannoth authored
Driver support to offload TC flower rules which matches against SPI field of IPSEC packets (AH/ESP). Signed-off-by:
Ratheesh Kannoth <rkannoth@marvell.com> Signed-off-by:
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Ratheesh Kannoth authored
This patch enables offload for TC classifier flower rules which matches against SPI field. Signed-off-by:
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Ratheesh Kannoth authored
tc flower rules support to classify ESP/AH packets matching SPI field. Signed-off-by:
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Ratheesh Kannoth authored
Support for dissecting IPSEC field SPI (which is 32bits in size) for ESP and AH packets. Signed-off-by:
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David S. Miller authored
Neil Armstrong says: ==================== net: ethernet: dwmac: oxnas glue removal With [1] removing MPCore SMP support, this makes the OX820 barely usable, associated with a clear lack of maintainance, development and migration to dt-schema it's clear that Linux support for OX810 and OX820 should be removed. In addition, the OX810 hasn't been booted for years and isn't even present in an ARM config file. For the OX820, lack of USB and SATA support makes the platform not usable in the current Linux support and relies on off-tree drivers hacked from the vendor (defunct for years) sources. The last users are in the OpenWRT distribution, and today's removal means support will still be in stable 6.1 LTS kernel until end of 2026. If someone wants to take over the development even with lack of SMP, I'll be happy to hand off maintainance. It has been a fun time adding support for this architecture, but it's time to get over! This patchset only removes net changes, and is derived from: https://lore.kernel.org/r/20230630-topic-oxnas-upstream-remove-v2-0-fb6ab3dea87c@linaro.org --- Changes in v3: - Removed applied changes - Added Andy's tags - Reduced for net - Link to v2: https://lore.kernel.org/r/20230630-topic-oxnas-upstream-remove-v2-0-fb6ab3dea87c@linaro.org Changes in v2: - s/maintainance/maintenance/ - added acked/review tags - dropped already applied patches - drop RFC - Link to v1: https://lore.kernel.org/r/20230331-topic-oxnas-upstream-remove-v1-0-5bd58fd1dd1f@linaro.org ==================== Signed-off-by:
Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by:
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Neil Armstrong authored
Due to lack of maintenance and stall of development for a few years now, and since no new features will ever be added upstream, remove the OX810 and OX820 dwmac glue. Acked-by:
Linus Walleij <linus.walleij@linaro.org> Acked-by:
Arnd Bergmann <arnd@arndb.de> Acked-by:
Daniel Golle <daniel@makrotopia.org> Acked-by:
Conor Dooley <conor.dooley@microchip.com> Signed-off-by:
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Neil Armstrong authored
Due to lack of maintenance and stall of development for a few years now, and since no new features will ever be added upstream, remove support for OX810 and OX820 ethernet. Acked-by:
Andy Shevchenko <andy@kernel.org> Signed-off-by:
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David S. Miller authored
Petr Machata says: ==================== selftests: New selftests for out-of-order-operations patches in mlxsw In the past, the mlxsw driver made the assumption that the user applies configuration in a bottom-up manner. Thus netdevices needed to be added to the bridge before IP addresses were configured on that bridge or SVI added on top of it, because whatever happened before a netdevice was mlxsw upper was generally ignored by mlxsw. Recently, several patch series were pushed to introduce the bookkeeping and replays necessary to offload the full state, not just the immediate configuration step. In this patchset, introduce new selftests that directly exercise the out of order code paths in mlxsw. - Patch #1 adds new tests into the existing selftest router_bridge.sh. - Patches #2-#5 add new generic selftests. - Patches #6-#8 add new mlxsw-specific selftests. ==================== Signed-off-by: -
Petr Machata authored
This test verifies driver behavior with regards to creation of RIFs for a bridge as LAGs are added or removed to/from it, and ports added or removed to/from the LAG. Signed-off-by:
Petr Machata <petrm@nvidia.com> Reviewed-by:
Danielle Ratson <danieller@nvidia.com> Signed-off-by:
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Petr Machata authored
This test verifies driver behavior with regards to creation of RIFs for LAG VLAN uppers as ports are added or removed to/from the LAG. Signed-off-by:
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Petr Machata authored
This test verifies driver behavior with regards to creation of RIFs for a LAG as ports are added or removed to/from it. Signed-off-by:
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Petr Machata authored
Add a selftest to verify that routing through several bridges works when LAG VLANs are used instead of physical ports, and that routing through LAG VLANs themselves works as physical ports are de/enslaved. Signed-off-by:
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Petr Machata authored
Add a selftest to verify that routing through a bridge works when LAG is used instead of physical ports. Signed-off-by:
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Petr Machata authored
Add a selftest that verifies routing through VLAN bridge uppers. Signed-off-by:
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Petr Machata authored
Add a selftest to verify that routing through a 1d bridge works when VLAN upper of a physical port is used instead of a physical port. Also verify that when a port is attached to an already-configured bridge, the configuration is applied. Signed-off-by:
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Petr Machata authored
Add two tests to deslave a port from and reenslave to a bridge. This should retain the ability of the system to forward traffic, but on an offloading driver that is sensitive to ordering of operations, it might not. The first test does this configuration in a way that relies on vlan_default_pvid to assign the PVID. The second test disables that autoconfiguration and configures PVID by hand in a separate step. Signed-off-by:
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Rohan G Thomas authored
For XGMAC versions < 2.2 number of supported mdio C22 addresses is restricted to 3. From XGMAC version 2.2 there are no restrictions on the C22 addresses, it supports all valid mdio addresses(0 to 31). Signed-off-by:
Rohan G Thomas <rohan.g.thomas@intel.com> Acked-by:
Jose Abreu <Jose.Abreu@synopsys.com> Signed-off-by:
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Jakub Kicinski authored
Radu Pirea says: ==================== Add TJA1120 support This patch series got bigger than I expected. It cleans up the next-c45-tja11xx driver and adds support for the TJA1120(1000BaseT1 automotive phy). Master/slave custom implementation was replaced with the generic implementation (genphy_c45_config_aneg/genphy_c45_read_status). The TJA1120 and TJA1103 are a bit different when it comes to the PTP interface. The timestamp read procedure was changed, some addresses were changed and some bits were moved from one register to another. Adding TJA1120 support was tricky, and I tried not to duplicate the code. If something looks too hacky to you, I am open to suggestions. ==================== Link: https://lore.kernel.org/r/20230731091619.77961-1-radu-nicolae.pirea@oss.nxp.comSigned-off-by:
Jakub Kicinski <kuba@kernel.org>
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Radu Pirea (NXP OSS) authored
During PTP testing on early TJA1120 engineering samples I observed that if the link is lost and recovered, the tx timestamps will be randomly lost. To avoid this HW issue, the PCS should be reset. Resetting the PCS will break the link and we should reset the PCS on LINK UP -> LINK DOWN transition, otherwise we will trigger and infinite loop of LINK UP -> LINK DOWN events. Signed-off-by:
Radu Pirea (NXP OSS) <radu-nicolae.pirea@oss.nxp.com> Reviewed-by:
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Radu Pirea (NXP OSS) authored
On TJA1120, the external trigger timestamp now has a VALID bit. This changes the logic and we can't use the TJA1103 procedure. For TJA1103, we can always read a valid timestamp from the registers, compare the new timestamp with the old timestamp and, if they are not the same, an event occurred. This logic cannot be applied for TJA1120 because the timestamp is 0 if the VALID bit is not set. Signed-off-by:
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Radu Pirea (NXP OSS) authored
For TJA1120, the enable bit for cable test is not writable if the PHY is not in test mode. Signed-off-by:
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Radu Pirea (NXP OSS) authored
TJA1120 and TJA1103 have a set of functional safety hardware tests executed after every reset, and when the tests are done, the IRQ line is asserted. For the moment, the purpose of these handlers is to acknowledge the IRQ and not to check the FUSA tests status. Signed-off-by:
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Radu Pirea (NXP OSS) authored
The egress timestamp FIFO/circular buffer work different on TJA1120 than TJA1103. For TJA1103 the new timestamp should be manually moved from the FIFO to the hardware buffer before checking if the timestamp is valid. For TJA1120 the hardware will move automatically the new timestamp from the FIFO to the buffer and the user should check the valid bit, read the timestamp and unlock the buffer by writing any of the buffer registers(which are read only). Another change for the TJA1120 is the behaviour of the EGR TS IRQ bit. This bit was a self-clear bit for TJA1103, but now should be cleared before reading the timestamp. Signed-off-by:
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Radu Pirea (NXP OSS) authored
The external trigger configuration for TJA1120 has changed. The PHY supports sampling of the LTC on rising and on falling edge. Signed-off-by:
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Radu Pirea (NXP OSS) authored
Add TJA1120 driver entry and its driver_data. Signed-off-by:
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Radu Pirea (NXP OSS) authored
PHY_BASIC_T1_FEATURES are not the right features supported by TJA1103 anymore. For example ethtool reports: [root@alarm ~]# ethtool end0 Settings for end0: Supported ports: [ TP ] Supported link modes: 100baseT1/Full 10baseT1L/Full 10baseT1L/Full is not supported by TJA1103 and supported ports list is not completed. The PHY also have a MII port. genphy_c45_pma_read_abilities implementation can detect the PHY features and they look like this. [root@alarm ~]# ethtool end0 Settings for end0: Supported ports: [ TP MII ] Supported link modes: 100baseT1/Full Supported pause frame use: Symmetric Supports auto-negotiation: No Supported FEC modes: Not reported Advertised link modes: 100baseT1/Full Advertised pause frame use: Symmetric Advertised auto-negotiation: No Advertised FEC modes: Not reported Speed: 100Mb/s Duplex: Full Auto-negotiation: off master-slave cfg: forced master master-slave status: master Port: Twisted Pair PHYAD: 1 Transceiver: external MDI-X: Unknown Supports Wake-on: g Wake-on: d Link detected: yes SQI: 7/7 Signed-off-by: -
Radu Pirea (NXP OSS) authored
Between TJA1120 and TJA1103 the hardware was improved, but some register addresses were changed and some bit fields were moved from one register to another. Introduce the nxp_c45_reg_field structure and its associated functions to abstract the differences between the PHYs. Remove the defined bits and register addresses that are not common between TJA1103 and TJA1120 and replace them with reg_fields and register addresses from phydev->drv->driver_data. Signed-off-by:
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Radu Pirea (NXP OSS) authored
Remove RX BIST frame counters from the PHY statistics. In production mode, these counters are always read as 0. Signed-off-by:
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Radu Pirea (NXP OSS) authored
Remove the custom implementation of master/save setup and read status and use genphy_c45_config_aneg and genphy_c45_read_status since phylib has support for master/slave setup and master/slave status. Signed-off-by:
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