- 15 Jun, 2018 36 commits
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Michel Dänzer authored
Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
Michel Dänzer <michel.daenzer@amd.com> Signed-off-by:
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Michel Dänzer authored
So that it can be referenced from e.g. DOC comments. Reviewed-by:
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Alex Deucher authored
Switch hawaii and bonaire to use powerplay rather than the old dpm implementation. Powerplay supports more features and is better maintained. Ultimately, we can drop the older dpm implementation like we did for other older asics. Reviewed-by:
Huang Rui <ray.huang@amd.com> Reviewed-by:
Rex Zhu <rezhu@amd.com> Signed-off-by:
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Alex Deucher authored
It's required for displays on Raven. The DCN bandwidth calcs use floating point, but DCN is APU only and it already depends on X86. Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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Alex Deucher authored
Just enable it always. This was leftover from feature bring up. Reviewed-by:
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Samuel Li authored
Document the GEM domains exposed to userspace. Suggested-by:
Samuel Li <Samuel.Li@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Samuel Li authored
Document the amdgpu buffer object API. v2: Add a DOC section and some more clarification. v3: Add some clarification and fix a spelling. Suggested-by:
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Tony Cheng authored
Signed-off-by:
Tony Cheng <tony.cheng@amd.com> Acked-by:
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Dmytro Laktyushkin authored
Signed-off-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by:
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Eric Bernstein authored
Update MSA MISC1 bit 6 programming to handle YCbCr 4:2:0 and BT2020 cases. Signed-off-by:
Eric Bernstein <eric.bernstein@amd.com> Reviewed-by:
Hersen Wu <hersenxs.wu@amd.com> Acked-by:
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Reza Amini authored
Signed-off-by:
Reza Amini <Reza.Amini@amd.com> Reviewed-by:
Aric Cyr <Aric.Cyr@amd.com> Acked-by:
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Tony Cheng authored
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Yasir Al Shekerchi authored
Signed-off-by:
Yasir Al Shekerchi <YasirAl.Shekerchi@amd.com> Reviewed-by:
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Vitaly Prosyak authored
Low level calculation methods. Signed-off-by:
Vitaly Prosyak <vitaly.prosyak@amd.com> Reviewed-by:
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Anthony Koo authored
Signed-off-by:
Anthony Koo <Anthony.Koo@amd.com> Reviewed-by:
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Krunoslav Kovac authored
Basic framework: - caps for reporting dynamic HDR metadata support - allocation of frame buffer memory and storage Signed-off-by:
Krunoslav Kovac <Krunoslav.Kovac@amd.com> Reviewed-by:
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Nikola Cornij authored
DP_SINK_STATUS_ESI range data is not continual, but rather than getting it in two AUX reads, it's quicker to read more bytes in a AUX read and then memcpy the required fields (it's only 8 more bytes to read). Signed-off-by:
Nikola Cornij <nikola.cornij@amd.com> Reviewed-by:
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Aric Cyr authored
Signed-off-by:
Jun Lei <Jun.Lei@amd.com> Reviewed-by:
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Hersen Wu authored
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Anthony Koo authored
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Eric Bernstein authored
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Hersen Wu authored
This change shorten wait time when HPD LOW. With HPD LOW, without this change, AUX routine delay is 450us. With this change, it is 42us. Signed-off-by:
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Anthony Koo authored
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Tony Cheng authored
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Dmytro Laktyushkin authored
This change will allow the viewport overlap to apply to rotated/ mirrored surfaces. Viewport overlap results in extra pixels being added to viewport allowing the first few pixels to be scaled as if there is no cut-off(mpo or pipe split) and allows us to get matching crc's between scaled split and unsplit outputs of the same thing. Signed-off-by:
Charlene Liu <Charlene.Liu@amd.com> Acked-by:
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Charlene Liu authored
Signed-off-by:
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Eric Bernstein authored
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Nayan Deshmukh authored
Signed-off-by:
Nayan Deshmukh <nayan26deshmukh@gmail.com> Reviewed-by:
Daniel Vetter <daniel@ffwll.ch> Signed-off-by:
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Nayan Deshmukh authored
convert existing raw comments into kernel-doc format as well as add new documentation v2: reword the overview Signed-off-by:
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Gustavo A. R. Silva authored
Currently, the maximum value that *counter* can reach is 255, and code at line 150: while (counter < 1000) { implies a bigger value could be expected. Fix this by changing the type of variable *counter* from uint8_t to uint16_t. Addresses-Coverity-ID: 1470030 ("Operands don't affect result") Fixes: 2b6199a1 ("drm/amd/display: replace msleep with udelay in fbc path") Signed-off-by:Gustavo A. R. Silva <gustavo@embeddedor.com> Signed-off-by:
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Alex Deucher authored
The uvd version information was not set correctly for vega20. Rearrange the logic to set it correctly and fix the warnings as a result. v2: fix version formatting for userspace based on feedback from Leo Fixes: 96ca7f298f (drm/amdgpu/vg20:support new UVD FW version naming convention) Reviewed-by:
Leo Liu <leo.liu@amd.com> Signed-off-by:
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James Zhu authored
Vega20 UVD Firmware has a new version naming convention: [31, 30] for encode interface major [29, 24] for encode interface minor [15, 8] for decode interface minor [7, 0] for hardware family id Signed-off-by:
James Zhu <James.Zhu@amd.com> Reviewed-by:
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Rex Zhu authored
if vbios not set the max clock voltage limit table for DC mode, Set the table as sama as the table for AC mode. Reviewed-by:
Rex Zhu <Rex.Zhu@amd.com> Signed-off-by:
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Rex Zhu authored
make custom values survive when S3 sleep transitions. so not reset the od table if it is not null. Reviewed-by:
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Christian König authored
Per VM BOs share the reservation object with the PD and so need to reserve a shared fence slot for the update. Signed-off-by:
Chunming Zhou <david1.zhou@amd.com> Reviewed-by:
Junwei Zhang <Jerry.Zhang@amd.com> Signed-off-by:
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git://people.freedesktop.org/~agd5f/linuxDave Airlie authored
Fixes for 4.18. Highlights: - Fixes for gfxoff on Raven - Remove an ATPX quirk now that the root cause is fixed - Runtime PM fixes - Vega20 register header update - Wattman fixes - Misc bug fixes Signed-off-by:
Dave Airlie <airlied@redhat.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180614141428.2909-1-alexander.deucher@amd.com
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- 14 Jun, 2018 1 commit
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Kenneth Feng authored
Fix the issue that SCLK&MCLK can't be set higher than dpm7 when OD is enabled in SMU7. v2: fix warning (Alex) Signed-off-by:
Kenneth Feng <kenneth.feng@amd.com> Acked-by: Rex Zhu<rezhu@amd.com> Signed-off-by:
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- 13 Jun, 2018 3 commits
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Evan Quan authored
Gfxoff is already enabled in amdgpu_device_ip_set_powergating_state. So, no need to enable it again in pp_late_init. Signed-off-by:
Evan Quan <evan.quan@amd.com> Reviewed-by:
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Evan Quan authored
WARN_ON possible buffer overflow and avoid unnecessary dereference. v2: change BUG_ON to WARN_ON Signed-off-by:
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Shaoyun Liu authored
The register field hsas been changed in df 3.6, update to correct setting Signed-off-by:
Shaoyun Liu <Shaoyun.Liu@amd.com> Acked-by:
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