Skip to content

GitLab

Switch branch/tag
  1. 15 Mar, 2011 1 commit
  3. 18 Jan, 2011 1 commit
  5. 24 Dec, 2010 1 commit
  7. 01 Dec, 2010 1 commit
  9. 10 Nov, 2010 2 commits
  11. 22 Oct, 2010 1 commit
    • Erik Gilling's avatar
      spi: add spi_tegra driver · 0c03a1dd
      Erik Gilling authored 
      
v2 changes:
  from Thierry Reding:
    * add "select TEGRA_SYSTEM_DMA" to Kconfig
  from Grant Likely:
    * add oneline description to header
    * inline references to DRIVER_NAME
    * inline references to BUSY_TIMEOUT
    * open coded bytes_per_word()
    * spi_readl/writel -> spi_tegra_readl/writel
    * move transfer validation to spi_tegra_transfer
    * don't request_mem_region iomem as platform bus does that for us
    * __exit -> __devexit

v3 changes:
  from Russell King:
    * put request_mem_region back int
  from Grant Likely:
    * remove #undef DEBUG
    * add SLINK_ to register bit defines
    * remove unused bytes_per_word
    * make spi_tegra_readl/writel static linine
    * various refactoring for clarity
    * mark err if BSY bit is not cleared after 1000 retries
    * move spinlock to protect setting of RDY bit
    * subsys_initcall -> module_init

v3 changes:
  from Grant Likely:
    * update spi_tegra to use PTR_ERRless dma API

v4 changes:
  from Grant Likely:
    * remove empty spi_tegra_cleanup fucntion
    * allow device ids of -1
Signed-off-by: default avatarErik Gilling <konkers@android.com>
Acked-by: default avatarGrant Likely <grant.likely@secretlab.ca>
Cc: Thierry Reding <thierry.reding@avionic-design.de>
Cc: Russell King <linux@arm.linux.org.uk>

spi: tegra: cleanups from upstream review

Change-Id: Icecf7e64efcb39de072a15234ba1faa4bad40d25
Signed-off-by: default avatarErik Gilling <konkers@android.com>
      0c03a1dd
  13. 13 Oct, 2010 4 commits
    • Mingkai Hu's avatar
      spi/fsl_spi: add eSPI controller support · 8b60d6c2
      Mingkai Hu authored 
      
Add eSPI controller support based on the library code spi_fsl_lib.c.

The eSPI controller is newer controller 85xx/Pxxx devices supported.
There're some differences comparing to the SPI controller:

1. Has different register map and different bit definition
   So leave the code operated the register to the driver code, not
   the common code.

2. Support 4 dedicated chip selects
   The software can't controll the chip selects directly, The SPCOM[CS]
   field is used to select which chip selects is used, and the
   SPCOM[TRANLEN] field is set to tell the controller how long the CS
   signal need to be asserted. So the driver doesn't need the chipselect
   related function when transfering data, just set corresponding register
   fields to controll the chipseclect.

3. Different Transmit/Receive FIFO access register behavior
   For SPI controller, the Tx/Rx FIFO access register can hold only
   one character regardless of the character length, but for eSPI
   controller, the register can hold 4 or 2 characters according to
   the character lengths. Access the Tx/Rx FIFO access register of the
   eSPI controller will shift out/in 4/2 characters one time. For SPI
   subsystem, the command and data are put into different transfers, so
   we need to combine all the transfers to one transfer in order to pass
   the transfer to eSPI controller.

4. The max transaction length limitation
   The max transaction length one time is limitted by the SPCOM[TRANSLEN]
   field which is 0xFFFF. When used mkfs.ext2 command to create ext2
   filesystem on the flash, the read length will exceed the max value of
   the SPCOM[TRANSLEN] field.
Signed-off-by: default avatarMingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: default avatarGrant Likely <grant.likely@secretlab.ca>
      8b60d6c2
    • Mingkai Hu's avatar
      spi/mpc8xxx: refactor the common code for SPI/eSPI controller · b36ece83
      Mingkai Hu authored 
      
Refactor the common code in file spi_fsl_spi.c to spi_fsl_lib.c used
by SPI/eSPI controller driver as a library, and leave the QE/CPM SPI
controller code in the SPI controller driver spi_fsl_spi.c.

Because the register map of the SPI controller and eSPI controller
is so different, also leave the code operated the register to the
driver code, not the common code.
Signed-off-by: default avatarMingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: default avatarGrant Likely <grant.likely@secretlab.ca>
      b36ece83
    • Mingkai Hu's avatar
      spi/mpc8xxx: rename spi_mpc8xxx.c to spi_fsl_spi.c · 3272029f
      Mingkai Hu authored 
      
This will pave the way to refactor out the common code which can be used
by the eSPI controller driver, and rename the SPI controller dirver to the
file spi_fsl_spi.c.
Signed-off-by: default avatarMingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: default avatarGrant Likely <grant.likely@secretlab.ca>
      3272029f
    • matt mooney's avatar
      spi: change to new flag variable · fadcf49b
      matt mooney authored 
      
Replace EXTRA_CFLAGS with ccflags-y.
Signed-off-by: default avatarmatt mooney <mfm@muteddisk.com>
Signed-off-by: default avatarGrant Likely <grant.likely@secretlab.ca>
      fadcf49b
  15. 08 Oct, 2010 1 commit
  17. 25 May, 2010 2 commits
  19. 21 Jan, 2010 1 commit
  21. 20 Jan, 2010 2 commits
  23. 17 Dec, 2009 3 commits
  25. 13 Dec, 2009 3 commits
    • Cory Maccarrone's avatar
      Add OMAP spi100k driver · 35c9049b
      Cory Maccarrone authored 
      
This change adds the OMAP SPI 100k driver created by
Fabrice Crohas <fcrohas@gmail.com>.  This SPI bus is found on
OMAP7xx-series smartphones, and for many, the touchscreen is
attached to this bus.

The lion's share of the work was done by Fabrice on this driver --
I am merely porting it from the Linwizard project on his behalf.
Signed-off-by: default avatarCory Maccarrone <darkstar6262@gmail.com>
Signed-off-by: default avatarGrant Likely <grant.likely@secretlab.ca>
      35c9049b
    • Wan ZongShun's avatar
      ARM: NUC900: Add spi driver support for nuc900 · 30eaed05
      Wan ZongShun authored 
      Signed-off-by: default avatarWan ZongShun <mcuos.com@gmail.com>
Signed-off-by: default avatarGrant Likely <grant.likely@secretlab.ca>
      30eaed05
    • Magnus Damm's avatar
      spi: SuperH MSIOF SPI Master driver V2 · 8051effc
      Magnus Damm authored 
      
This patch is V2 of SPI Master support for the SuperH MSIOF.
Full duplex, spi mode 0-3, active high cs, 3-wire and lsb
first should all be supported, but the driver has so far
only been tested with "mmc_spi".

The MSIOF hardware comes with 32-bit FIFOs for receive and
transmit, and this driver simply breaks the SPI messages
into FIFO-sized chunks. The MSIOF hardware manages the pins
for clock, receive and transmit (sck/miso/mosi), but the chip
select pin is managed by software and must be configured as
a regular GPIO pin by the board code.

Performance wise there is still room for improvement, but
on a Ecovec board with the built-in sh7724 MSIOF0 this driver
gets Mini-sd read speeds of about half a megabyte per second.

Future work include better clock setup and merging of 8-bit
transfers into 32-bit words to reduce interrupt load and
improve throughput.
Signed-off-by: default avatarMagnus Damm <damm@opensource.se>
Signed-off-by: default avatarGrant Likely <grant.likely@secretlab.ca>
      8051effc
  27. 09 Dec, 2009 2 commits
  29. 04 Nov, 2009 1 commit
  31. 01 Oct, 2009 1 commit
  33. 23 Sep, 2009 4 commits
  35. 19 Jun, 2009 2 commits
  37. 10 Jun, 2009 1 commit
  39. 26 Jan, 2009 1 commit
  41. 06 Jan, 2009 1 commit
    • David Brownell's avatar
      spi_gpio driver · d29389de
      David Brownell authored 
      
Generalize the old at91rm9200 "bootstrap" bitbanging SPI master driver as
"spi_gpio", so it works with arbitrary GPIOs and can be configured through
platform_data.  Such SPI masters support:

 - any number of bus instances (bus_num is the platform_device.id)
 - any number of chipselects (one GPIO per spi_device)
 - all four SPI_MODE values, and SPI_CS_HIGH
 - i/o word sizes from 1 to 32 bits;
 - devices configured as with any other spi_master controller

When configured using platform_data, this provides relatively low clock
rates.  On platforms that support inlined GPIO calls, significantly
improved transfer speeds are also possible with a semi-custom driver.
(It's still painful when accessing flash memory, but less so.)

Sanity checked by using this version to replace both native controllers on
a board with six different SPI slaves, relying on three different
SPI_MODE_* values and both SPI_CS_HIGH settings for correct operation.

[akpm@linux-foundation.org: cleanups]
Signed-off-by: default avatarDavid Brownell <dbrownell@users.sourceforge.net>
Acked-by: default avatarMagnus Damm <damm@igel.co.jp>
Tested-by: default avatarMagnus Damm <damm@igel.co.jp>
Cc: Torgil Svensson <torgil.svensson@gmail.com>
Signed-off-by: default avatarAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: default avatarLinus Torvalds <torvalds@linux-foundation.org>
      d29389de
  43. 05 Aug, 2008 1 commit
  45. 06 Feb, 2008 1 commit
  47. 17 Jul, 2007 2 commits
GitLab Nexedi Edition | About GitLab | About Nexedi | 沪ICP备2021021310号-2 | 沪ICP备2021021310号-7