- 01 Jun, 2020 3 commits
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Stephen Boyd authored
* clk-unisoc: clk: sprd: add mipi_csi_xx gate clocks clk: sprd: add dt-bindings include for mipi_csi_xx clocks dt-bindings: clk: sprd: add mipi_csi_xx clocks for SC9863A clk: sprd: check its parent status before reading gate clock clk: sprd: return correct type of value for _sprd_pll_recalc_rate clk: sprd: mark the local clock symbols static * clk-trivial: clk: versatile: remove redundant assignment to pointer clk clk: clk-xgene: Fix a typo in Kconfig clk: Remove unused inline function clk_debug_reparent * clk-bcm: clk: bcm2835: Constify struct debugfs_reg32 clk: bcm2835: Remove casting to bcm2835_clk_register clk: bcm2835: Fix return type of bcm2835_register_gate * clk-st: clk: clk-flexgen: fix clock-critical handling * clk-ast2600: clk: ast2600: Fix AHB clock divider for A1
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Stephen Boyd authored
Merge branches 'clk-tegra', 'clk-imx', 'clk-zynq', 'clk-socfpga', 'clk-at91' and 'clk-ti' into clk-next - Support custom flags in Xilinx zynq firmware - Various small fixes to the Xilinx clk driver - Support for Intel Agilex clks * clk-tegra: clk: tegra: Add Tegra210 CSI TPG clock gate clk: tegra30: Use custom CCLK implementation clk: tegra20: Use custom CCLK implementation clk: tegra: cclk: Add helpers for handling PLLX rate changes clk: tegra: pll: Add pre/post rate-change hooks clk: tegra: Add custom CCLK implementation clk: tegra: Remove the old emc_mux clock for Tegra210 clk: tegra: Implement Tegra210 EMC clock clk: tegra: Export functions for EMC clock scaling clk: tegra: Add PLLP_UD and PLLMB_UD for Tegra210 clk: tegra: Rename Tegra124 EMC clock source file dt-bindings: clock: tegra: Add clock ID for CSI TPG clock * clk-imx: clk: imx: use imx8m_clk_hw_composite_bus for i.MX8M bus clk slice clk: imx: add imx8m_clk_hw_composite_bus clk: imx: add mux ops for i.MX8M composite clk clk: imx8m: migrate A53 clk root to use composite core clk: imx8mp: use imx8m_clk_hw_composite_core to simplify code clk: imx8mp: Define gates for pll1/2 fixed dividers clk: imx: imx8mp: fix pll mux bit clk: imx8m: drop clk_hw_set_parent for A53 dt-bindings: clocks: imx8mp: Add ids for audiomix clocks clk: imx: Add helpers for passing the device as argument clk: imx: pll14xx: Add the device as argument when registering clk: imx: gate2: Allow single bit gating clock clk: imx: clk-pllv3: Use readl_relaxed_poll_timeout() for PLL lock wait clk: imx: clk-sscg-pll: Remove unnecessary blank lines clk: imx: drop the dependency on ARM64 for i.MX8M clk: imx7ulp: make it easy to change ARM core clk clk: imx: imx6ul: change flexcan clock to support CiA bitrates * clk-zynq: clk: zynqmp: Make zynqmp_clk_get_max_divisor static clk: zynqmp: Update fraction clock check from custom type flags clk: zynqmp: Add support for custom type flags clk: zynqmp: fix memory leak in zynqmp_register_clocks clk: zynqmp: Fix invalid clock name queries clk: zynqmp: Fix divider2 calculation clk: zynqmp: Limit bestdiv with maxdiv * clk-socfpga: clk: socfpga: agilex: add clock driver for the Agilex platform dt-bindings: documentation: add clock bindings information for Agilex clk: socfpga: add const to _ops data structures clk: socfpga: remove clk_ops enable/disable methods clk: socfpga: stratix10: use new parent data scheme * clk-at91: clk: at91: allow setting all PMC clock parents via DT clk: at91: allow setting PCKx parent via DT clk: at91: optimize pmc data allocation clk: at91: pmc: decrement node's refcount clk: at91: pmc: do not continue if compatible not located clk: at91: Add peripheral clock for PTC * clk-ti: clk: ti: dra7: remove two unused symbols clk: ti: dra7xx: fix RNG clock parent clk: ti: dra7xx: mark MCAN clock as DRA76x only clk: ti: dra7xx: fix gpu clkctrl parent clk: ti: omap5: Add proper parent clocks for l4-secure clocks clk: ti: omap4: Add proper parent clocks for l4-secure clocks clk: ti: composite: fix memory leak
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Stephen Boyd authored
Merge branches 'clk-selectable', 'clk-amlogic', 'clk-renesas', 'clk-samsung' and 'clk-allwinner' into clk-next - Allow the COMMON_CLK config to be selectable * clk-selectable: clk: Move HAVE_CLK config out of architecture layer MIPS: Loongson64: Drop asm/clock.h include ARM: mmp: Remove legacy clk code clk: Allow the common clk framework to be selectable mmc: meson-mx-sdio: Depend on OF_ADDRESS and not just OF MIPS: Remove redundant CLKDEV_LOOKUP selects h8300: Remove redundant CLKDEV_LOOKUP selects arm64: tegra: Remove redundant CLKDEV_LOOKUP selects ARM: Remove redundant CLKDEV_LOOKUP selects ARM: Remove redundant COMMON_CLK selects * clk-amlogic: clk: meson: meson8b: Don't rely on u-boot to init all GP_PLL registers clk: meson: meson8b: Make the CCF use the glitch-free VPU mux clk: meson: meson8b: Fix the vclk_div{1, 2, 4, 6, 12}_en gate bits clk: meson: meson8b: Fix the polarity of the RESET_N lines clk: meson: meson8b: Fix the first parent of vid_pll_in_sel clk: meson: g12a: Prepare the GPU clock tree to change at runtime clk: meson: gxbb: Prepare the GPU clock tree to change at runtime clk: meson: meson8b: make the hdmi_sys clock tree mutable clk: meson8b: export the HDMI system clock * clk-renesas: dt-bindings: clock: renesas: mstp: Convert to json-schema dt-bindings: clock: renesas: div6: Convert to json-schema clk: renesas: cpg-mssr: Fix STBCR suspend/resume handling clk: renesas: rcar-gen2: Remove superfluous CLK_RENESAS_DIV6 selects clk: renesas: cpg-mssr: Add R8A7742 support dt-bindings: clock: renesas: cpg-mssr: Document r8a7742 binding clk: renesas: Add r8a7742 CPG Core Clock Definitions dt-bindings: power: rcar-sysc: Add r8a7742 power domain index macros MAINTAINERS: Add DT Bindings for Renesas Clock Generators clk: renesas: r9a06g032: Fix some typo in comments dt-bindings: clock: renesas: rcar-usb2-clock-sel: Add r8a77961 support * clk-samsung: clk: samsung: exynos5433: Add IGNORE_UNUSED flag to sclk_i2s1 ARM/SAMSUNG EXYNOS ARM ARCHITECTURES: Use fallthrough; clk: samsung: Fix CLK_SMMU_FIMCL3 clock name on Exynos542x clk: samsung: Mark top ISP and CAM clocks on Exynos542x as critical * clk-allwinner: clk: sunxi: Fix incorrect usage of round_down()
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- 27 May, 2020 29 commits
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Eddie James authored
The latest specs for the AST2600 A1 chip include some different bit definitions for calculating the AHB clock divider. Implement these in order to get the correct AHB clock value in Linux. Signed-off-by:
Eddie James <eajames@linux.ibm.com> Link: https://lkml.kernel.org/r/20200408203616.4031-1-eajames@linux.ibm.com Fixes: d3d04f6c ("clk: Add support for AST2600 SoC") Signed-off-by:
Stephen Boyd <sboyd@kernel.org>
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Alain Volmat authored
Fixes an issue leading to having all clocks following a critical clocks marked as well as criticals. Fixes: fa6415af ("clk: st: clk-flexgen: Detect critical clocks") Signed-off-by:
Alain Volmat <avolmat@me.com> Link: https://lkml.kernel.org/r/20200322140740.3970-1-avolmat@me.comReviewed-by:
Patrice Chotard <patrice.chotard@st.com> Signed-off-by:
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Rikard Falkeborn authored
bcm2835_debugfs_clock_reg32 is never changed and can therefore be made const. This allows the compiler to put it in the text section instead of the data section. Before: text data bss dec hex filename 26598 16088 64 42750 a6fe drivers/clk/bcm/clk-bcm2835.o After: text data bss dec hex filename 26662 16024 64 42750 a6fe drivers/clk/bcm/clk-bcm2835.o Signed-off-by:
Rikard Falkeborn <rikard.falkeborn@gmail.com> Link: https://lkml.kernel.org/r/20200508220238.4883-1-rikard.falkeborn@gmail.comSigned-off-by:
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Chunyan Zhang authored
mipi_csi_xx clocks are used by camera sensors. Signed-off-by:
Chunyan Zhang <chunyan.zhang@unisoc.com> Link: https://lkml.kernel.org/r/20200527053638.31439-5-zhang.lyra@gmail.comSigned-off-by:
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Chunyan Zhang authored
mipi_csi_xx clocks are used by camera sensors. Signed-off-by:
Rob Herring <robh@kernel.org> Link: https://lkml.kernel.org/r/20200527053638.31439-4-zhang.lyra@gmail.comSigned-off-by:
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Chunyan Zhang authored
mipi_csi_xx clocks are used by camera sensors. Signed-off-by:
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Chunyan Zhang authored
Some clocks only can be accessed if their parent is enabled. mipi_csi_xx clocks on SC9863A are an examples. We have to ensure the parent clock is enabled when reading those clocks. Signed-off-by:
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Colin Ian King authored
The pointer clk is being initialized with a value that is never read and is being updated with a new value later on. The initialization is redundant and can be removed. Addresses-Coverity: ("Unused value") Signed-off-by:Colin Ian King <colin.king@canonical.com> Link: https://lkml.kernel.org/r/20200526224116.63549-1-colin.king@canonical.comReviewed-by:
Linus Walleij <linus.walleij@linaro.org> Signed-off-by:
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Jason Yan authored
Fix the following gcc warning: drivers/clk/ti/clk-7xx.c:320:43: warning: ‘dra7_gpu_sys_clk_data’ defined but not used [-Wunused-const-variable=] static const struct omap_clkctrl_div_data dra7_gpu_sys_clk_data __initconst = { ^~~~~~~~~~~~~~~~~~~~~ drivers/clk/ti/clk-7xx.c:315:27: warning: ‘dra7_gpu_sys_clk_parents’ defined but not used [-Wunused-const-variable=] static const char * const dra7_gpu_sys_clk_parents[] __initconst = { ^~~~~~~~~~~~~~~~~~~~~~~~ Reported-by:Hulk Robot <hulkci@huawei.com> Signed-off-by:
Jason Yan <yanaijie@huawei.com> Link: https://lkml.kernel.org/r/20200417073523.42520-1-yanaijie@huawei.comAcked-by:
Tony Lindgren <tony@atomide.com> Signed-off-by:
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Michał Mirosław authored
We need to have clocks accessible via phandle to select them as peripheral clock parent using assigned-clock-parents in DT. Add support for PLLACK/PLLBCK/AUDIOPLLCK clocks where available. Signed-off-by:
Michał Mirosław <mirq-linux@rere.qmqm.pl> Acked-by:
Alexandre Belloni <alexandre.belloni@bootlin.com> Link: https://lkml.kernel.org/r/fa39cc10dab8341ea4bc2b7152be9217b2cd34a5.1588630999.git.mirq-linux@rere.qmqm.plSigned-off-by:
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Michał Mirosław authored
This exposes PROGx clocks for use in assigned-clocks DeviceTree property for selecting PCKx parent clock. Signed-off-by:
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Michał Mirosław authored
Alloc whole data structure in one block. This makes the code shorter, more efficient and easier to extend in following patch. Signed-off-by:
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Claudiu Beznea authored
of_find_matching_node() increment node's refcount. Call of_node_put() to decrement it after it was used. Signed-off-by:
Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lkml.kernel.org/r/1588508289-10140-2-git-send-email-claudiu.beznea@microchip.comSigned-off-by:
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Claudiu Beznea authored
pmc_register_ops() is called for all AT91 devices. Return -ENODEV in case of_find_matching_node() returns NULL. Signed-off-by:
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Codrin Ciubotariu authored
PMC generates the peripheral clock for the PTC. Signed-off-by:
Codrin Ciubotariu <codrin.ciubotariu@microchip.com> Link: https://lkml.kernel.org/r/20200515142720.290206-1-codrin.ciubotariu@microchip.comSigned-off-by:
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Chunyan Zhang authored
The function _sprd_pll_recalc_rate() defines return value to unsigned long, but it would return a negative value when malloc fail, changing to return its parent_rate makes more sense, since if the callback .recalc_rate() is not set, the framework returns the parent_rate as well. Fixes: 3e37b005 ("clk: sprd: add adjustable pll support") Signed-off-by:
Baolin Wang <baolin.wang7@gmail.com> Signed-off-by:
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Chunyan Zhang authored
There's a few pll gate clocks which were not marked with static, and those clock are used only in the current file, so add static key word for them. Fixes: 0e4b8a23 ("clk: sprd: add clocks support for SC9863A") Signed-off-by:
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Dinh Nguyen authored
For the most part the Agilex clock structure is very similar to Stratix10, so we re-use most of the Stratix10 clock driver. Signed-off-by:
Dinh Nguyen <dinguyen@kernel.org> Link: https://lkml.kernel.org/r/20200512181647.5071-5-dinguyen@kernel.orgSigned-off-by:
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Dinh Nguyen authored
Document the Agilex clock bindings, and add the clock header file. The clock header is an enumeration of all the different clocks on the Agilex platform. Signed-off-by:
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Dinh Nguyen authored
All the static clk_ops data structure need a const. Signed-off-by:
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Dinh Nguyen authored
The enable/disable clock ops are already defined in the standard clock ops, so we don't need to assign them. Signed-off-by:
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Dinh Nguyen authored
Convert, where possible, the stratix10 clock driver to the new parent data scheme by specifying the parent data for clocks that have multiple parents. Signed-off-by:
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YueHaibing authored
Fix sparse warning: drivers/clk/zynqmp/divider.c:259:5: warning: symbol 'zynqmp_clk_get_max_divisor' was not declared. Should it be static? Reported-by:
YueHaibing <yuehaibing@huawei.com> Link: https://lkml.kernel.org/r/20200403083040.37748-1-yuehaibing@huawei.comReviewed-by:
Michal Simek <michal.simek@xilinx.com> Signed-off-by:
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Tejas Patel authored
Older firmware version sets BIT(13) in clkflag to mark a divider as fractional divider. Updated firmware version sets BIT(4) in type flags to mark a divider as fractional divider since BIT(13) is defined as CLK_DUTY_CYCLE_PARENT in the common clk framework flags. To support both old and new firmware version, consider BIT(13) from clkflag and BIT(4) from type_flag to check if divider is fractional or not. To maintain compatibility BIT(13) of clkflag in firmware will not be used in future for any purpose and will be marked as unused. Signed-off-by:
Tejas Patel <tejas.patel@xilinx.com> Signed-off-by:
Rajan Vaja <rajan.vaja@xilinx.com> Signed-off-by:
Jolly Shah <jolly.shah@xilinx.com> Link: https://lkml.kernel.org/r/1584048699-24186-3-git-send-email-jolly.shah@xilinx.comSigned-off-by:
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Rajan Vaja authored
Store extra custom type flags received from firmware. Signed-off-by:
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Quanyang Wang authored
This is detected by kmemleak running on zcu102 board: unreferenced object 0xffffffc877e48180 (size 128): comm "swapper/0", pid 1, jiffies 4294892909 (age 315.436s) hex dump (first 32 bytes): 64 70 5f 76 69 64 65 6f 5f 72 65 66 5f 64 69 76 dp_video_ref_div 31 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 1............... backtrace: [<00000000c9be883b>] __kmalloc_track_caller+0x200/0x380 [<00000000f02c3809>] kvasprintf+0x7c/0x100 [<00000000e51dde4d>] kasprintf+0x60/0x80 [<0000000092298b05>] zynqmp_register_clocks+0x29c/0x398 [<00000000faaff182>] zynqmp_clock_probe+0x3cc/0x4c0 [<000000005f5986f0>] platform_drv_probe+0x58/0xa8 [<00000000d5810136>] really_probe+0xd8/0x2a8 [<00000000f5b671be>] driver_probe_device+0x5c/0x100 [<0000000038f91fcf>] __device_attach_driver+0x98/0xb8 [<000000008a3f2ac2>] bus_for_each_drv+0x74/0xd8 [<000000001cb2783d>] __device_attach+0xe0/0x140 [<00000000c268031b>] device_initial_probe+0x24/0x30 [<000000006998de4b>] bus_probe_device+0x9c/0xa8 [<00000000647ae6ff>] device_add+0x3c0/0x610 [<0000000071c14bb8>] of_device_add+0x40/0x50 [<000000004bb5d132>] of_platform_device_create_pdata+0xbc/0x138 This is because that when num_nodes is larger than 1, clk_out is allocated using kasprintf for these nodes but only the last node's clk_out is freed. Signed-off-by:
Quanyang Wang <quanyang.wang@windriver.com> Signed-off-by:
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Rajan Vaja authored
The clock driver makes EEMI call to get the name of invalid clk when executing versal_get_clock_info() function. This results in error messages. Added check for validating clock before saving clock attribute and calling zynqmp_pm_clock_get_name() in versal_get_clock_info() function. Signed-off-by:
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Tejas Patel authored
zynqmp_get_divider2_val() calculates, divider value of type DIV2 clock, considering best possible combination of DIV1 and DIV2. To find best possible values of DIV1 and DIV2, DIV1's parent rate should be consider and not DIV2's parent rate since it would rate of div1 clock. Consider a below topology, out_clk->div2_clk->div1_clk->fixed_parent where out_clk = (fixed_parent/div1_clk) / div2_clk, so parent clock of div1_clk (i.e. out_clk) should be divided by div1_clk and div2_clk. Existing code divides parent rate of div2_clk's clock instead of div1_clk's parent rate, which is wrong. Fix the same by considering div1's parent clock rate. Fixes: 4ebd92d2 ("clk: zynqmp: Fix divider calculation") Signed-off-by:
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Rajan Vaja authored
Clock divider value should not be greater than maximum divider value. So use minimum of best divider or maximum divider value. Signed-off-by:
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- 26 May, 2020 3 commits
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Nathan Chancellor authored
There are four different callback functions that are used for the clk_register callback that all have different second parameter types. bcm2835_register_pll -> struct bcm2835_pll_data bcm2835_register_pll_divider -> struct bcm2835_pll_divider_data bcm2835_register_clock -> struct bcm2835_clock_data bcm2835_register_date -> struct bcm2835_gate_data These callbacks are cast to bcm2835_clk_register so that there is no error about incompatible pointer types. Unfortunately, this is a control flow integrity violation, which verifies that the callback function's types match the prototypes exactly before jumping. [ 0.857913] CFI failure (target: 0xffffff9334a81820): [ 0.857977] WARNING: CPU: 3 PID: 35 at kernel/cfi.c:29 __cfi_check_fail+0x50/0x58 [ 0.857985] Modules linked in: [ 0.858007] CPU: 3 PID: 35 Comm: kworker/3:1 Not tainted 4.19.123-v8-01301-gdbb48f16956e4-dirty #1 [ 0.858015] Hardware name: Raspberry Pi 3 Model B Rev 1.2 (DT) [ 0.858031] Workqueue: events 0xffffff9334a925c8 [ 0.858046] pstate: 60000005 (nZCv daif -PAN -UAO) [ 0.858058] pc : __cfi_check_fail+0x50/0x58 [ 0.858070] lr : __cfi_check_fail+0x50/0x58 [ 0.858078] sp : ffffff800814ba90 [ 0.858086] x29: ffffff800814ba90 x28: 000fffffffdfff3d [ 0.858101] x27: 00000000002000c2 x26: ffffff93355fdb18 [ 0.858116] x25: 0000000000000000 x24: ffffff9334a81820 [ 0.858131] x23: ffffff93357f3580 x22: ffffff9334af1000 [ 0.858146] x21: a79b57e88f8ebc81 x20: ffffff93357f3580 [ 0.858161] x19: ffffff9334a81820 x18: fffffff679769070 [ 0.858175] x17: 0000000000000000 x16: 0000000000000000 [ 0.858190] x15: 0000000000000004 x14: 000000000000003c [ 0.858205] x13: 0000000000003044 x12: 0000000000000000 [ 0.858220] x11: b57e91cd641bae00 x10: b57e91cd641bae00 [ 0.858235] x9 : b57e91cd641bae00 x8 : b57e91cd641bae00 [ 0.858250] x7 : 0000000000000000 x6 : ffffff933591d4e5 [ 0.858264] x5 : 0000000000000000 x4 : 0000000000000000 [ 0.858279] x3 : ffffff800814b718 x2 : ffffff9334a84818 [ 0.858293] x1 : ffffff9334bba66c x0 : 0000000000000029 [ 0.858308] Call trace: [ 0.858321] __cfi_check_fail+0x50/0x58 [ 0.858337] __cfi_check+0x3ab3c/0x4467c [ 0.858351] bcm2835_clk_probe+0x210/0x2dc [ 0.858369] platform_drv_probe+0xb0/0xfc [ 0.858380] really_probe+0x4a0/0x5a8 [ 0.858391] driver_probe_device+0x68/0x104 [ 0.858403] __device_attach_driver+0x100/0x148 [ 0.858418] bus_for_each_drv+0xb0/0x12c [ 0.858431] __device_attach.llvm.17225159516306086099+0xc0/0x168 [ 0.858443] bus_probe_device+0x44/0xfc [ 0.858455] deferred_probe_work_func+0xa0/0xe0 [ 0.858472] process_one_work+0x210/0x538 [ 0.858485] worker_thread+0x2e8/0x478 [ 0.858500] kthread+0x154/0x164 [ 0.858515] ret_from_fork+0x10/0x18 To fix this, change the second parameter of all functions void * and use a local variable with the correct type so that everything works properly. With this, the only use of bcm2835_clk_register is in struct bcm2835_clk_desc so we can just remove it and use the type directly. Fixes: 56eb3a2e ("clk: bcm2835: remove use of BCM2835_CLOCK_COUNT in driver") Link: https://github.com/ClangBuiltLinux/linux/issues/1028Signed-off-by:
Nathan Chancellor <natechancellor@gmail.com> Link: https://lkml.kernel.org/r/20200516080806.1459784-2-natechancellor@gmail.comSigned-off-by:
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Nathan Chancellor authored
bcm2835_register_gate is used as a callback for the clk_register member of bcm2835_clk_desc, which expects a struct clk_hw * return type but bcm2835_register_gate returns a struct clk *. This discrepancy is hidden by the fact that bcm2835_register_gate is cast to the typedef bcm2835_clk_register by the _REGISTER macro. This turns out to be a control flow integrity violation, which is how this was noticed. Change the return type of bcm2835_register_gate to be struct clk_hw * and use clk_hw_register_gate to do so. This should be a non-functional change as clk_register_gate calls clk_hw_register_gate anyways but this is needed to avoid issues with further changes. Fixes: b19f009d ("clk: bcm2835: Migrate to clk_hw based registration and OF APIs") Link: https://github.com/ClangBuiltLinux/linux/issues/1028Signed-off-by:
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Stephen Boyd authored
Merge tag 'clk-imx-5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into clk-imx Pull i.MX clk driver updates from Shawn Guo: - A few patches from Abel Vesa as preparation of adding audiomix clock support - A couple of cleanups from Anson Huang on clk-sscg-pll and clk-pllv3 driver - Update imx7ulp clock driver to use imx_clk_hw_cpu() for making the change of ARM core clock easier - Drop dependency on ARM64 for i.MX8M clock driver, as there is a move to support aarch32 mode on aarch64 hardware - A series from Peng Fan to improve i.MX8M clock drivers, using composite clock for core and bus clk slice - Set a better parent clock for flexcan on i.MX6UL to support CiA102 defined bit rates * tag 'clk-imx-5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: clk: imx: use imx8m_clk_hw_composite_bus for i.MX8M bus clk slice clk: imx: add imx8m_clk_hw_composite_bus clk: imx: add mux ops for i.MX8M composite clk clk: imx8m: migrate A53 clk root to use composite core clk: imx8mp: use imx8m_clk_hw_composite_core to simplify code clk: imx8mp: Define gates for pll1/2 fixed dividers clk: imx: imx8mp: fix pll mux bit clk: imx8m: drop clk_hw_set_parent for A53 dt-bindings: clocks: imx8mp: Add ids for audiomix clocks clk: imx: Add helpers for passing the device as argument clk: imx: pll14xx: Add the device as argument when registering clk: imx: gate2: Allow single bit gating clock clk: imx: clk-pllv3: Use readl_relaxed_poll_timeout() for PLL lock wait clk: imx: clk-sscg-pll: Remove unnecessary blank lines clk: imx: drop the dependency on ARM64 for i.MX8M clk: imx7ulp: make it easy to change ARM core clk clk: imx: imx6ul: change flexcan clock to support CiA bitrates
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- 21 May, 2020 5 commits
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git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linuxStephen Boyd authored
Pull Tegra clk driver updates from Thierry Reding: These are a couple of changes to implement EMC frequency scaling on Tegra210, CPU frequency scaling on Tegra20 and Tegra30 as well as a special clock gate for the CSI test pattern generator on Tegra210. * tag 'for-5.8-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: clk: tegra: Add Tegra210 CSI TPG clock gate clk: tegra30: Use custom CCLK implementation clk: tegra20: Use custom CCLK implementation clk: tegra: cclk: Add helpers for handling PLLX rate changes clk: tegra: pll: Add pre/post rate-change hooks clk: tegra: Add custom CCLK implementation clk: tegra: Remove the old emc_mux clock for Tegra210 clk: tegra: Implement Tegra210 EMC clock clk: tegra: Export functions for EMC clock scaling clk: tegra: Add PLLP_UD and PLLMB_UD for Tegra210 clk: tegra: Rename Tegra124 EMC clock source file dt-bindings: clock: tegra: Add clock ID for CSI TPG clock
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Stephen Boyd authored
Merge tag 'sunxi-clk-for-5.8-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-allwinner Pull an Allwinner clk driver fix from Maxime Ripard: - a single minor rounding fix for the legacy Allwinner clock support * tag 'sunxi-clk-for-5.8-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: clk: sunxi: Fix incorrect usage of round_down()
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Stephen Boyd authored
Merge tag 'clk-v5.8-samsung' of https://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk into clk-samsung Pull Samsung clk driver updates from Sylwester Nawrocki: - Regression fixes for exynos542x and exynos5433 SoCs - use of fallthrough; attribute for s3c24xx * tag 'clk-v5.8-samsung' of https://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk: clk: samsung: exynos5433: Add IGNORE_UNUSED flag to sclk_i2s1 ARM/SAMSUNG EXYNOS ARM ARCHITECTURES: Use fallthrough; clk: samsung: Fix CLK_SMMU_FIMCL3 clock name on Exynos542x clk: samsung: Mark top ISP and CAM clocks on Exynos542x as critical
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Stephen Boyd authored
Merge tag 'clk-renesas-for-v5.8-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas Pull Renesas clk driver updates from Geert Uytterhoeven: - A minor fix for the currently unused suspend/resume handling on RZ/A1 and RZ/A2 - Two more conversions of Renesas DT bindings to json-schema * tag 'clk-renesas-for-v5.8-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: dt-bindings: clock: renesas: mstp: Convert to json-schema dt-bindings: clock: renesas: div6: Convert to json-schema clk: renesas: cpg-mssr: Fix STBCR suspend/resume handling
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Peng Fan authored
Switch the bus clk use imx8m_clk_hw_composite_bus, then we could avoid possible issue when setting mux of the clk. Signed-off-by:
Peng Fan <peng.fan@nxp.com> Reviewed-by:
Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by:
Shawn Guo <shawnguo@kernel.org>
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