- 05 Mar, 2020 32 commits
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Aric Cyr authored
Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Acked-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Bhawanpreet Lakha authored
[Why] If we have a single MST display and we disconnect it, we dont disable that link. This causes the old link settings to still exist Now on a replug for MST we think its a link loss and will try to reallocate mst payload which will fail, throwing warning below. [ 129.374192] [drm] Failed to updateMST allocation table forpipe idx:0 [ 129.374206] ------------[ cut here ]------------ [ 129.374284] WARNING: CPU: 14 PID: 1710 at drivers/gpu/drm/amd/amdgpu/../dal-dev/dc/core/dc_link.c:3153 dc_link_allocate_mst_payload+0x1f7/0x220 [amdgpu] [ 129.374285] Modules linked in: amdgpu(OE) amd_iommu_v2 gpu_sched ttm drm_kms_helper drm fb_sys_fops syscopyarea sysfillrect sysimgblt binfmt_misc nls_iso8859_1 edac_mce_amd snd_hda_codec_realtek snd_hda_codec_generic ledtrig_audio kvm snd_hda_codec_hdmi snd_hda_intel snd_intel_nhlt snd_hda_codec irqbypass snd_hda_core snd_hwdep snd_pcm snd_seq_midi snd_seq_midi_event snd_rawmidi crct10dif_pclmul snd_seq crc32_pclmul ghash_clmulni_intel snd_seq_device snd_timer snd aesni_intel eeepc_wmi crypto_simd asus_wmi joydev cryptd sparse_keymap input_leds soundcore video glue_helper wmi_bmof mxm_wmi k10temp ccp mac_hid sch_fq_codel parport_pc ppdev lp parport ip_tables x_tables autofs4 hid_generic usbhid hid igb i2c_algo_bit ahci dca i2c_piix4 libahci gpio_amdpt wmi gpio_generic [ 129.374318] CPU: 14 PID: 1710 Comm: kworker/14:2 Tainted: G W OE 5.4.0-rc7bhawan+ #480 [ 129.374318] Hardware name: System manufacturer System Product Name/PRIME X370-PRO, BIOS 0515 03/30/2017 [ 129.374397] Workqueue: events dm_irq_work_func [amdgpu] [ 129.374468] RIP: 0010:dc_link_allocate_mst_payload+0x1f7/0x220 [amdgpu] [ 129.374470] Code: 52 20 e8 1c 63 ad f4 48 8b 5d d0 65 48 33 1c 25 28 00 00 00 b8 01 00 00 00 75 16 48 8d 65 d8 5b 41 5c 41 5d 41 5e 41 5f 5d c3 <0f> 0b e9 fa fe ff ff e8 ed 5b d6 f3 41 0f b6 b6 c4 02 00 00 48 c7 [ 129.374471] RSP: 0018:ffff9f9141e7fcc0 EFLAGS: 00010246 [ 129.374472] RAX: 0000000000000000 RBX: ffff91ef0762f800 RCX: 0000000000000000 [ 129.374473] RDX: 0000000000000005 RSI: ffffffffc0c4a988 RDI: 0000000000000004 [ 129.374474] RBP: ffff9f9141e7fd10 R08: 0000000000000005 R09: 0000000000000000 [ 129.374475] R10: 0000000000000002 R11: 0000000000000001 R12: ffff91eebd510c00 [ 129.374475] R13: ffff91eebd510e58 R14: ffff91ef052c01b8 R15: 0000000000000006 [ 129.374476] FS: 0000000000000000(0000) GS:ffff91ef0ef80000(0000) knlGS:0000000000000000 [ 129.374477] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 129.374478] CR2: 000055623ea01d50 CR3: 0000000408a8c000 CR4: 00000000003406e0 [ 129.374479] Call Trace: [ 129.374550] dc_link_reallocate_mst_payload+0x12e/0x150 [amdgpu] [ 129.374617] dc_link_handle_hpd_rx_irq+0x6d4/0x6e0 [amdgpu] [ 129.374693] handle_hpd_rx_irq+0x77/0x310 [amdgpu] [ 129.374768] dm_irq_work_func+0x53/0x70 [amdgpu] [ 129.374774] process_one_work+0x1fd/0x3f0 [ 129.374776] worker_thread+0x255/0x410 [ 129.374778] kthread+0x121/0x140 [ 129.374780] ? process_one_work+0x3f0/0x3f0 [ 129.374781] ? kthread_park+0x90/0x90 [ 129.374785] ret_from_fork+0x22/0x40 [How] when we disable MST we should clear the cur link settings (lane_count=0 is good enough). This will cause us to not reallocate payloads earlier than expected and not throw the warning Signed-off-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by:
Hersen Wu <hersenxs.wu@amd.com> Acked-by:
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Nikola Cornij authored
Disabling FEC for specific monitors is sometimes required for debugging while in the monitor bringup phase Signed-off-by:
Nikola Cornij <nikola.cornij@amd.com> Reviewed-by:
Alvin Lee <Alvin.Lee2@amd.com> Acked-by:
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Sung Lee authored
[WHY] We see an issue that caused clk_optimized_required to be set true in certain cases, causing passive flips to fail. This is because of a typo where wm_optimized_required was set twice. [HOW] Set clk_optimized_required to false after updating clocks. Signed-off-by:
Sung Lee <sung.lee@amd.com> Reviewed-by:
Tony Cheng <Tony.Cheng@amd.com> Acked-by:
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Yongqiang Sun authored
[Why] vstartup calculation is incorrect due to use 2 number of cursors and result in an underflow when playing video in full screen mode and combines graphic plane and video plane. [How] Apply new policy for dml calculation. 1 cursor for graphic plane, 0 cursor for video plane. Signed-off-by:
Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by:
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Josip Pavic authored
[Why] Swath sizes are being calculated incorrectly. The horizontal swath size should be the product of block height, viewport width, and bytes per element, but the calculation uses viewport height instead of width. The vertical swath size is similarly incorrectly calculated. The effect of this is that we report the wrong DCC caps. [How] Use viewport width in the horizontal swath size calculation and viewport height in the vertical swath size calculation. Signed-off-by:
Josip Pavic <Josip.Pavic@amd.com> Reviewed-by:
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Michael Strauss authored
[WHY] Freesync borderless is not meant to be enabled on any APUs [HOW] Add is_apu cap to dcn21_resource_construct for correct recognition Signed-off-by:
Michael Strauss <michael.strauss@amd.com> Reviewed-by:
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Sung Lee authored
[WHY] SMU FW previously had an issue with lowering display clock to below 100 MHz, and a workaround was put in to limit it. Newest SMU FW does not have this issue, and no longer needs the 100MHz cap. [HOW] Remove the 100MHz cap based on the SMU FW version. Signed-off-by:
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George Shen authored
[Why] When transitioning from SST to MST, the HDCP repeater in some MST displays will enter a bad state. The HDCP repeater is recovered after failing and performing authentication again. [How] Add monitor patch to trigger HDCP authentication failure after encryption is enabled and re-authenticate. Signed-off-by:
George Shen <george.shen@amd.com> Reviewed-by:
Wenjing Liu <Wenjing.Liu@amd.com> Acked-by:
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Wenjing Liu authored
[why] When combining two or more pipes in DSC mode, there will always be more than 1 slice per line. In this case, as per DSC rules, the sink device is expecting that the ICH is reset at the end of each slice line (i.e. ICH_RESET_AT_END_OF_LINE must be configured based on the number of slices at the output of ODM). It is recommended that software set ICH_RESET_AT_END_OF_LINE = 0xF for each DSC in the ODM combine. However the current code only set ICH_RESET_AT_END_OF_LINE = 0xF when number of slice per DSC engine is greater than 1 instead of number of slice per output after ODM combine. [how] Add is_odm in dsc config. Set ICH_RESET_AT_END_OF_LINE = 0xF if either is_odm or number of slice per DSC engine is greater than 1. Signed-off-by:
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Wenjing Liu authored
[why] When test pattern is enabled with ODM combine, test pattern is generated by piecing multiple DPGs image together. The current code will program all DPGs with horizontal offset of 0. This will cause all DPGs to output the beginning of the pattern. Instead each DPG should program a horizontal offset of its x position to form a continous pattern when pieced together. Signed-off-by:
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Wenjing Liu authored
[how] Allow vsc info packet if vsc is supported. Update vsc based on test pattern request. Remove dpg_is_blanked polling, apply hardware global lock instead to ensure double buffered dpg is updated with vsc in one frame Signed-off-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
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Roman Li authored
[Why] Typo in amdgpu_dm error message: "Failed to found connector for link!" [How] 1. Replace with: "Failed to find connector for link!" 2. Fix indentation checkpatch warnings. Signed-off-by:
Roman Li <roman.li@amd.com> Reviewed-by:
Zhan Liu <Zhan.Liu@amd.com> Acked-by:
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Sung Lee authored
[WHY & HOW] In order to correctly intepret clock table, num_states is also needed. This field did not get moved with clock_table but should next to it for easier access/viewing. Signed-off-by:
Eric Yang <eric.yang2@amd.com> Acked-by:
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Joseph Gravenor authored
[why] When we have single channel memory, we can not light up 2 4k displays with a 1080p edp, because we don't have enough bw by a small margin. this small margin comes from dcc meta being too large. We however don't have this dcc meta when we create fake planes so, before the flip we will not filter out the mode for 2 4k displays with a 1080p edp [how] Change get_default_swizzle_mode to something more general so we don't end up with a separate function for every missing field in the fake plane. Add a reasonable dcc meta to the fake plane when it is filled in, so we filter out modes that don't have enough bandwidth. To do this, we take the screen width and align it to 1024(8k 60) Signed-off-by:
Joseph Gravenor <joseph.gravenor@amd.com> Reviewed-by:
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Wenjing Liu authored
[why] Some asics don't support FEC but FEC overhead is added into link bandwidth calculation by mistake. This causes certain timing cannot be validated. [how] Only include FEC overhead if both asic and display support FEC. Signed-off-by:
Ashley Thomas <Ashley.Thomas2@amd.com> Acked-by:
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Wyatt Wood authored
[Why] We want to be able to enable PSR on DMCUB, and fallback to DMCU when necessary. [How] Move psr_on_dmub flag from dc_debug_options to dc_config. Signed-off-by:
Wyatt Wood <wyatt.wood@amd.com> Reviewed-by:
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Isabel Zhang authored
[Why] Reset connection is called before remove display in mod_hdcp. When remove display is called, the display structure has been zeroed from reset connection. Since no displays can be found, remove display does not properly reset the hardware. This causes validation errors when another display is plugged into a different port afterwards. [How] Moved displays structure out of connections structure. Displays structure is now directly within mod_hdcp. Displays is no longer zeroed when reset connection is called. Signed-off-by:
Isabel Zhang <isabel.zhang@amd.com> Reviewed-by:
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Martin Leung authored
[Why] Previously implemented early_cr_pattern we mistook dp_hw_link_settings for a redundant call of dpcd_set_link_settings [How] revert the changes to dpcd_set_link_settings calls for this workaround. Do not need to revert the entire change since it only affects patched case Signed-off-by:
Martin Leung <martin.leung@amd.com> Reviewed-by:
David Galiffi <David.Galiffi@amd.com> Acked-by:
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Samir Dhume authored
Ported from Vega10. SDMA stress tests sometimes see IRQ lost. Signed-off-by:
Samir Dhume <samir.dhume@amd.com> Reviewed-by:
Monk Liu <monk.liu@amd.com> Signed-off-by:
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Monk Liu authored
scratch_reg0 is used by RLCG for register access usage in SRIOV case. both CP firmware and driver can invoke RLCG to do certain register access (through scratch_reg0/1/2/3) but rlcg now dosen't have race concern so if two clients are in parallel doing the RLCG reg access then we are colliding, GFX IB test is a runtime work, so it is forbidden to use scrach_reg0/1/2/3 during IB test period note: Although we can only have this change for SRIOV, but looks it doesn't worth the effort to differentiate bare-metal with SRIOV on the GFX ib test Signed-off-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Monk Liu authored
1)for gfx IB test we shouldn't insert DE meta data 2)we should make sure IB test finished before we send event 3 to hypervisor otherwise the IDLE from event 3 will preempt IB test, which is not designed as a compatible structure for MCBP Signed-off-by:
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Tianci.Yin authored
[why] CP firmware decide to skip setting the state for 3D pipe 1 for Navi1x as there is no use case. [how] Disable 3D pipe 1 on Navi1x. Reviewed-by:
Feifei Xu <Feifei.Xu@amd.com> Reviewed-by:
Tianci.Yin <tianci.yin@amd.com> Signed-off-by:
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Chengming Gui authored
add debugfs interface amdgpu_force_sclk to set arbitrary sclk for navi14 v2: Add lock Signed-off-by:
Chengming Gui <Jack.Gui@amd.com> Reviewed-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
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Chengming Gui authored
Add lock_needed param for smu_set_soft_freq_range() Signed-off-by:
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Melissa Wen authored
Removes codestyle issues on detect_dp function as suggested by checkpatch.pl. CHECK: Lines should not end with a '(' WARNING: Missing a blank line after declarations WARNING: line over 80 characters CHECK: Alignment should match open parenthesis Signed-off-by:Melissa Wen <melissa.srw@gmail.com> Reviewed-by:
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Melissa Wen authored
Coding style clean up on enable_link_dp function as suggested by checkpatch.pl: CHECK: Lines should not end with a '(' WARNING: line over 80 characters WARNING: suspect code indent for conditional statements (8, 24) CHECK: braces {} should be used on all arms of this statement ERROR: else should follow close brace '}' CHECK: Comparison to NULL could be written "link->preferred_training_settings.fec_enable" Signed-off-by: -
Dan Carpenter authored
This is freeing the wrong variable so it will crash. It should be freeing "*dmub" instead of "dmub". Fixes: 4c1a1335 ("drm/amd/display: Driverside changes to support PSR in DMCUB") Reviewed-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by:
Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by:
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Colin Ian King authored
There are multiple statements that are indented incorrectly. Add in the missing tabs. Signed-off-by:
Colin Ian King <colin.king@canonical.com> Signed-off-by:
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Colin Ian King authored
There is a statement that is indented with spaces instead of a tab. Replace spaces with a tab. Signed-off-by:
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Rohit Khaire authored
This change programs CP_ME_CNTL and RLC_CSIB_* through RLC Signed-off-by:
Rohit Khaire <Rohit.Khaire@amd.com> Reviewed-by:
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Yintian Tao authored
The TDR will be randomly failed due to compute ring test failure. If the compute ring wptr & 0x7ff(ring_buf_mask) is 0x100 then after map mqd the compute ring rptr will be synced with 0x100. And the ring test packet size is also 0x100. Then after invocation of amdgpu_ring_commit, the cp will not really handle the packet on the ring buffer because rptr is equal to wptr. Signed-off-by:
Yintian Tao <yttao@amd.com> Acked-by:
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- 28 Feb, 2020 8 commits
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Matt Coffin authored
This adds a message lock to the smu_send_smc_msg* implementations to protect against concurrent access to the mmu registers used to communicate with the SMU v2: Implement for smu_v12_0 as well v3: Add mutex_init for message_lock Signed-off-by:
Matt Coffin <mcoffin13@gmail.com> Signed-off-by:
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Matt Coffin authored
The new interface reads the argument in the call to send the message, so this is no longer needed, and shouldn't be used for concurrency safety reasons. Signed-off-by:
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Matt Coffin authored
Move the responsibility for reading argument registers into the smu_send_smc_msg* implementations, so that adding a message-sending lock to protect the SMU registers will result in the lock still being held when the argument is read. v2: transition smu_v12_0, it's asics, and vega20 Signed-off-by:
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Hersen Wu authored
dc to pplib interface is changed for navi1x, renoir. display_config_changed is not called by dc anymore. smu_write_watermarks_table is not executed for navi1x, renoir during boot up. solution: call smu_write_watermarks_table just after dc pass watermark clock settings to pplib Signed-off-by:
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Yintian Tao authored
If we release drm_device before amdgpu_driver_unload_kms, then it will raise the error below. Therefore, we need to place it before amdgpu_driver_unload_kms. [ 43.055736] Memory manager not clean during takedown. [ 43.055777] WARNING: CPU: 1 PID: 2807 at /build/linux-hwe-9KJ07q/linux-hwe-4.18.0/drivers/gpu/drm/drm_mm.c:913 drm_mm_takedown+0x24/0x30 [drm] [ 43.055778] Modules linked in: amdgpu(OE-) amd_sched(OE) amdttm(OE) amdkcl(OE) amd_iommu_v2 drm_kms_helper drm i2c_algo_bit fb_sys_fops syscopyarea sysfillrect sysimgblt snd_hda_codec_generic nfit kvm_intel kvm irqbypass crct10dif_pclmul crc32_pclmul snd_hda_intel snd_hda_codec snd_hda_core snd_hwdep snd_pcm ghash_clmulni_intel snd_seq_midi snd_seq_midi_event pcbc snd_rawmidi snd_seq snd_seq_device aesni_intel snd_timer joydev aes_x86_64 crypto_simd cryptd glue_helper snd soundcore input_leds mac_hid serio_raw qemu_fw_cfg binfmt_misc sch_fq_codel nfsd auth_rpcgss nfs_acl lockd grace sunrpc parport_pc ppdev lp parport ip_tables x_tables autofs4 hid_generic floppy usbhid psmouse hid i2c_piix4 e1000 pata_acpi [ 43.055819] CPU: 1 PID: 2807 Comm: modprobe Tainted: G OE 4.18.0-15-generic #16~18.04.1-Ubuntu [ 43.055820] Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS 1.12.0-1 04/01/2014 [ 43.055830] RIP: 0010:drm_mm_takedown+0x24/0x30 [drm] [ 43.055831] Code: 84 00 00 00 00 00 0f 1f 44 00 00 48 8b 47 38 48 83 c7 38 48 39 c7 75 02 f3 c3 55 48 c7 c7 38 33 80 c0 48 89 e5 e8 1c 41 ec d0 <0f> 0b 5d c3 0f 1f 84 00 00 00 00 00 0f 1f 44 00 00 55 48 89 e5 41 [ 43.055857] RSP: 0018:ffffae33c1393d28 EFLAGS: 00010286 [ 43.055859] RAX: 0000000000000000 RBX: ffff9651b4a29800 RCX: 0000000000000006 [ 43.055860] RDX: 0000000000000007 RSI: 0000000000000096 RDI: ffff9651bfc964b0 [ 43.055861] RBP: ffffae33c1393d28 R08: 00000000000002a6 R09: 0000000000000004 [ 43.055861] R10: ffffae33c1393d20 R11: 0000000000000001 R12: ffff9651ba6cb000 [ 43.055863] R13: ffff9651b7f40000 R14: ffffffffc0de3a10 R15: ffff9651ba5c6460 [ 43.055864] FS: 00007f1d3c08d540(0000) GS:ffff9651bfc80000(0000) knlGS:0000000000000000 [ 43.055865] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 43.055866] CR2: 00005630a5831640 CR3: 000000012e274004 CR4: 00000000003606e0 [ 43.055870] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 [ 43.055871] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400 [ 43.055871] Call Trace: [ 43.055885] drm_vma_offset_manager_destroy+0x1b/0x30 [drm] [ 43.055894] drm_gem_destroy+0x19/0x40 [drm] [ 43.055903] drm_dev_fini+0x7f/0x90 [drm] [ 43.055911] drm_dev_release+0x2b/0x40 [drm] [ 43.055919] drm_dev_unplug+0x64/0x80 [drm] [ 43.055994] amdgpu_pci_remove+0x39/0x70 [amdgpu] [ 43.055998] pci_device_remove+0x3e/0xc0 [ 43.056001] device_release_driver_internal+0x18a/0x260 [ 43.056003] driver_detach+0x3f/0x80 [ 43.056004] bus_remove_driver+0x59/0xd0 [ 43.056006] driver_unregister+0x2c/0x40 [ 43.056008] pci_unregister_driver+0x22/0xa0 [ 43.056087] amdgpu_exit+0x15/0x57c [amdgpu] [ 43.056090] __x64_sys_delete_module+0x146/0x280 [ 43.056094] do_syscall_64+0x5a/0x120 v2: put drm_dev_put after pci_set_drvdata Signed-off-by:
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Yintian Tao authored
drm_minor_unregister will invoke drm_debugfs_cleanup to clean all the child node under primary minor node. We don't need to invoke amdgpu_debugfs_fini and amdgpu_debugfs_regs_cleanup to clean agian. Otherwise, it will raise the NULL pointer like below. [ 45.046029] BUG: unable to handle kernel NULL pointer dereference at 00000000000000a8 [ 45.047256] PGD 0 P4D 0 [ 45.047713] Oops: 0002 [#1] SMP PTI [ 45.048198] CPU: 0 PID: 2796 Comm: modprobe Tainted: G W OE 4.18.0-15-generic #16~18.04.1-Ubuntu [ 45.049538] Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS 1.12.0-1 04/01/2014 [ 45.050651] RIP: 0010:down_write+0x1f/0x40 [ 45.051194] Code: 90 66 2e 0f 1f 84 00 00 00 00 00 0f 1f 44 00 00 55 48 89 e5 53 48 89 fb e8 ce d9 ff ff 48 ba 01 00 00 00 ff ff ff ff 48 89 d8 <f0> 48 0f c1 10 85 d2 74 05 e8 53 1c ff ff 65 48 8b 04 25 00 5c 01 [ 45.053702] RSP: 0018:ffffad8f4133fd40 EFLAGS: 00010246 [ 45.054384] RAX: 00000000000000a8 RBX: 00000000000000a8 RCX: ffffa011327dd814 [ 45.055349] RDX: ffffffff00000001 RSI: 0000000000000001 RDI: 00000000000000a8 [ 45.056346] RBP: ffffad8f4133fd48 R08: 0000000000000000 R09: ffffffffc0690a00 [ 45.057326] R10: ffffad8f4133fd58 R11: 0000000000000001 R12: ffffa0113cff0300 [ 45.058266] R13: ffffa0113c0a0000 R14: ffffffffc0c02a10 R15: ffffa0113e5c7860 [ 45.059221] FS: 00007f60d46f9540(0000) GS:ffffa0113fc00000(0000) knlGS:0000000000000000 [ 45.060809] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 45.061826] CR2: 00000000000000a8 CR3: 0000000136250004 CR4: 00000000003606f0 [ 45.062913] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 [ 45.064404] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400 [ 45.065897] Call Trace: [ 45.066426] debugfs_remove+0x36/0xa0 [ 45.067131] amdgpu_debugfs_ring_fini+0x15/0x20 [amdgpu] [ 45.068019] amdgpu_debugfs_fini+0x2c/0x50 [amdgpu] [ 45.068756] amdgpu_pci_remove+0x49/0x70 [amdgpu] [ 45.069439] pci_device_remove+0x3e/0xc0 [ 45.070037] device_release_driver_internal+0x18a/0x260 [ 45.070842] driver_detach+0x3f/0x80 [ 45.071325] bus_remove_driver+0x59/0xd0 [ 45.071850] driver_unregister+0x2c/0x40 [ 45.072377] pci_unregister_driver+0x22/0xa0 [ 45.073043] amdgpu_exit+0x15/0x57c [amdgpu] [ 45.073683] __x64_sys_delete_module+0x146/0x280 [ 45.074369] do_syscall_64+0x5a/0x120 [ 45.074916] entry_SYSCALL_64_after_hwframe+0x44/0xa9 v2: remove all debugfs cleanup/fini code at amdgpu v3: squash in unused variable removal Signed-off-by:
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Jacob He authored
SPM_VMID is a global resource, SPM access the video memory according to SPM_VMID. The initial valude of SPM_VMID is 0 which is used by kernel. That means UMD can overwrite the memory of VMID0 by enabling SPM, that is really dangerous. Initialize SPM_VMID with 0xf, it messes up other user mode process at most. v2: squash in indentation fix Signed-off-by:
Jacob He <jacob.he@amd.com> Reviewed-by:
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Emily Deng authored
For vega10 sriov, the register is blocked, use copy data command to fix the issue. v2: Rename amdgpu_kiq_read_clock to gfx_v9_0_kiq_read_clock. Signed-off-by:
Emily Deng <Emily.Deng@amd.com> Reviewed-by:
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