- 29 Sep, 2012 40 commits
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Brian Norris authored
Instead of reading 2 bytes then later 8 bytes, we can simply read all 8 bytes from the start. Signed-off-by:
Brian Norris <computersforpeace@gmail.com> Signed-off-by:
Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by:
David Woodhouse <David.Woodhouse@intel.com>
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Brian Norris authored
We don't actually use the 'ret' variable; we set it, test it, and then it dies. Signed-off-by:
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Peter Huewe authored
While building an allyesconfig for UML I received this error message(s): drivers/mtd/nand/docg4.c: In function 'probe_docg4': drivers/mtd/nand/docg4.c:1272:2: error: implicit declaration of function 'ioremap' [-Werror=implicit-function-declaration] drivers/mtd/nand/docg4.c:1272:10: warning: assignment makes pointer from integer without a cast [enabled by default] drivers/mtd/nand/docg4.c:1327:2: error: implicit declaration of function 'iounmap' [-Werror=implicit-function-declaration] which is caused by the missing implementations on UML. This patch adds this missing HAS_IOMEM dependency and prevents the driver from being build on platforms with no HAS_IOMEM Signed-off-by:
Peter Huewe <peterhuewe@gmx.de> Acked-by:
Mike Dunn <mikedunn@newsguy.com> Signed-off-by:
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Huang Shijie authored
The current code initializes the timing registers at very time we call the gpmi_begin(). This really wastes the cpu cycles. Add a new flag to let the gpmi driver initializes the timing registers only one time. Signed-off-by:
Huang Shijie <b32955@freescale.com> Signed-off-by:
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Huang Shijie authored
When the frequency on the nand chip pins is above 33MHz, the nand EDO(extended Data Out) timing could be applied. The GPMI implements a Feedback read strobe to sample the read data in the EDO timing mode. This patch adds the EDO feature for the gpmi-nand driver. For some onfi nand chips, the mode 4 is the fastest; while for other onfi nand chips, the mode 5 is the fastest. This patch only adds the support for the fastest asynchronous timing mode. So this patch only supports the mode 4 and mode 5. I tested several Micron's ONFI nand chips with EDO enabled, take Micron MT29F32G08MAA for example (in mode 5, 100MHz): 1) The test result BEFORE we add the EDO feature: ================================================= mtd_speedtest: MTD device: 2 mtd_speedtest: MTD device size 209715200, eraseblock size 524288, page size 4096, count of eraseblocks 400, pages per eraseblock 128, OOB size 218 ....................................... mtd_speedtest: testing eraseblock read speed mtd_speedtest: eraseblock read speed is 3632 KiB/s ....................................... mtd_speedtest: testing page read speed mtd_speedtest: page read speed is 3554 KiB/s ....................................... mtd_speedtest: testing 2 page read speed mtd_speedtest: 2 page read speed is 3592 KiB/s ....................................... ================================================= 2) The test result AFTER we add the EDO feature: ================================================= mtd_speedtest: MTD device: 2 mtd_speedtest: MTD device size 209715200, eraseblock size 524288, page size 4096, count of eraseblocks 400, pages per eraseblock 128, OOB size 218 ....................................... mtd_speedtest: testing eraseblock read speed mtd_speedtest: eraseblock read speed is 19555 KiB/s ....................................... mtd_speedtest: testing page read speed mtd_speedtest: page read speed is 17319 KiB/s ....................................... mtd_speedtest: testing 2 page read speed mtd_speedtest: 2 page read speed is 18339 KiB/s ....................................... ================================================= 3) The read data performance is much improved by more then 5 times. Signed-off-by:
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Huang Shijie authored
The default frequencies of the extra clocks are 200MHz. The current code sets the extra clocks to 44.5MHz. When i add the EDO feature to gpmi, i have to revert the extra clocks to 200MHz. So it is better that we do not set the default values for the extra clocks. The driver runs well even when we do not set the default values for extra clocks. Signed-off-by:
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Huang Shijie authored
The setting DLL code is a little mess. Just simplify the code and the comments. Signed-off-by:
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Huang Shijie authored
add the WRN_DLY_SEL field for HW_GPMI_CTRL1. This field is used as delay for gpmi write strobe. Signed-off-by:
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Huang Shijie authored
The current code will gets the clock frequency which is used by gpmi_nfc_compute_hardware_timing(). It makes the code a little mess. So move the `get clock frequency` code to the gpmi_nfc_compute_hardware_timing() itself. This makes the code tidy and clean. This patch also uses the macro NSEC_PER_SEC to replace the `1000000000`. Signed-off-by:
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Huang Shijie authored
The gpmi_nfc_compute_hardware_timing{} should contains all the fields setting for gpmi timing registers. It already contains the fields for HW_GPMI_TIMING0 and HW_GPMI_CTRL1. So it is better to add a new field setting for HW_GPMI_TIMING1 in this data structure. This makes the code more clear in logic. This patch also changes some comments to make the code more readable. Signed-off-by: -
Huang Shijie authored
add onfi_get_async_timing_mode() to get the supportted asynchronous timing mode. add onfi_get_sync_timing_mode() to get the supportted synchronous timing mode. Also add the neccessary macros : the timing modes. Signed-off-by:
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Huang Shijie authored
Add the set-features(0xef)/get-features(0xee) helpers for ONFI nand. Also add the necessary macros. Signed-off-by:
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Kim Phillips authored
drivers/mtd/nand/fsl_ifc_nand.c:196:34: warning: cast removes address space of expression [sparse] drivers/mtd/nand/fsl_ifc_nand.c:196:34: warning: incorrect type in initializer (different address spaces) [sparse] drivers/mtd/nand/fsl_ifc_nand.c:196:34: expected unsigned int [noderef] [usertype] <asn:2>*mainarea [sparse] drivers/mtd/nand/fsl_ifc_nand.c:196:34: got unsigned int [usertype] *<noident> [sparse] ... Signed-off-by:
Kim Phillips <kim.phillips@freescale.com> Signed-off-by:
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Richard Genoud authored
If override size is too big, the module was actually loaded instead of failing, because retval was not set. This lead to memory corruption with the use of the freed structs nandsim and nand_chip. Cc: stable@vger.kernel.org Signed-off-by:
Richard Genoud <richard.genoud@gmail.com> Signed-off-by:
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Mike Dunn authored
Currently the docg4's ecc.read_page() method returns -EBADMSG when uncorrectable bitflips occur. This is wrong; 0 should be returned in this case. An error code should only be returned by this method in the case of a hardware error (probably -EIO). Signed-off-by:
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Richard Genoud authored
In nand_bbt.c, a hardcoded value was used instead of the define meant for that, so we use the define. There's no functional change. Signed-off-by:
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Christian Daudt authored
This driver is being removed as part of the cleanup of the bcmring SoC from mainline as it is no longer maintained. Signed-off-by:
Christian Daudt <csd@broadcom.com> Reviewed-by:
Jiandong Zheng <jdzheng@broadcom.com> Acked-by:
Will Deacon <will.deacon@arm.com> Signed-off-by:
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Mike Dunn authored
In the absence of any formal documentation of the nand interface, I thought this patch to the header file might be helpful. Signed-off-by:
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m-karicheri2@ti.com authored
As a first step towards migrating davinci platforms to use common clock framework, replace all instances of clk_enable() with clk_prepare_enable() and clk_disable() with clk_disable_unprepare(). Until the platform is switched to use the CONFIG_HAVE_CLK_PREPARE Kconfig variable, this just adds a might_sleep() call and would work without any issues. This will make it easy later to switch to common clk based implementation of clk driver from DaVinci specific driver. Signed-off-by:
Murali Karicheri <m-karicheri2@ti.com> Reviewed-by:
Mike Turquette <mturquette@linaro.org> Acked-by:
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Akinobu Mita authored
This adds the double bit error detection test cases listed below: * Prepare data block with double bit error and ECC data without corruption, and verify that the uncorrectable error is detected by __nand_correct_data(). * Prepare data block with single bit error and ECC data with single bit error, and verify that the uncorrectable error is detected. * Prepare data block without corruption and ECC data with double bit error, and verify that the uncorrectable error is detected. Signed-off-by:
Akinobu Mita <akinobu.mita@gmail.com> Signed-off-by:
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Akinobu Mita authored
This adds the single bit error correction test case listed below: Prepare data block without corruption and ECC data with single bit error, and verify that the data block is preserved by __nand_correct_data(). Signed-off-by:
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Akinobu Mita authored
This adds no corruptin test case listed below: Prepare data block and ECC data with no corruption, and verify that the data block is preserved by __nand_correct_data() Signed-off-by:
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Akinobu Mita authored
This rewrites the entire test routine in order to make it easy to add more tests by later changes and minimize duplication of each tests as much as possible. Now that each test is described by the members of struct nand_ecc_test: - name: descriptive testname - prepare: function to prepare data block and ecc with artifical corruption - verify: function to verify the result of correcting data block Signed-off-by:
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Akinobu Mita authored
Currently inject_single_bit_error() is used to inject single bit error into randomly selected bit position of the 256 or 512 bytes data block. Later change will add tests which inject bit errors into the ecc code. Unfortunately, inject_single_bit_error() doesn't work for the ecc code which is not a multiple of sizeof(unsigned long). Because bit fliping at random position is done by __change_bit(). For example, flipping bit position 0 by __change_bit(0, addr) modifies 3rd byte (32bit) or 7th byte (64bit) on big-endian systems. Using little-endian version of bitops can fix this issue. But little-endian version of __change_bit is not yet available. So this defines __change_bit_le() locally in a similar fashion to asm-generic/bitops/le.h and use it. Signed-off-by:
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Iwo Mergler authored
This tests ECC biterror recovery on a single NAND page. Mostly intended to test ECC hardware and low-level NAND driver. There are two test modes: 0 - artificially inserting bit errors until the ECC fails This is the default method and fairly quick. It should be independent of the quality of the FLASH. 1 - re-writing the same pattern repeatedly until the ECC fails. This method relies on the physics of NAND FLASH to eventually generate '0' bits if '1' has been written sufficient times. Depending on the NAND, the first bit errors will appear after 1000 or more writes and then will usually snowball, reaching the limits of the ECC quickly. The test stops after 10000 cycles, should your FLASH be exceptionally good and not generate bit errors before that. Try a different page offset in that case. Please note that neither of these tests will significantly 'use up' any FLASH endurance. Only a maximum of two erase operations will be performed. Signed-off-by:Iwo Mergler <Iwo.Mergler@netcommwireless.com.au> Signed-off-by:
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Shmulik Ladkani authored
Huang Shijie <shijie8@gmail.com> explains: Assume we have a 1GiB(8Gib) NAND chip, and we set the partitions in the command line like this: #gpmi-nand:100m(boot),100m(kernel),1g(rootfs) In this case, the partition truncating occurs. The current code will get the following result: ---------------------------------- root@freescale ~$ cat /proc/mtd dev: size erasesize name mtd0: 06400000 00040000 "boot" mtd1: 06400000 00040000 "kernel" ---------------------------------- It is obvious that we lost the truncated partition `rootfs` which should be 824MiB in this case. Also, forbid 0-sized partitions. Signed-off-by:Shmulik Ladkani <shmulik.ladkani@gmail.com> Signed-off-by:
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Sachin Kamat authored
module_platform_driver simplifies the code by eliminating module_init and module_exit calls. Signed-off-by:
Sachin Kamat <sachin.kamat@linaro.org> Signed-off-by:
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Fabio Estevam authored
With the new i.mx clock framework the mxc_nand clock is registered as: clk_register_clkdev(clk[nfc_gate], NULL, "mxc_nand");0") So we do not need to pass "nfc" string and can use NULL instead. Signed-off-by:
Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by:
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Fabio Estevam authored
Using module_platform_driver() makes the code smaller and cleaner. Signed-off-by:
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Fabio Estevam authored
Using module_platform_driver() makes the code smaller and cleaner. Signed-off-by:
Marek Vasut <marex@denx.de> Signed-off-by:
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Fabio Estevam authored
Improve logging style by prefixing the pr_ messages with "gpmi_nand". Signed-off-by:
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Marek Vasut authored
Quoting from the datasheet for S25FL064P, rev. 05, Nov 18 2011, § 9.17: "A 64 kB[sic] sector erase (D8h) command issued on 4 kB or 8 kB erase sectors will erase all sectors in the specified 64 kB region. However, please note that a 4 kB sector erase (20h) or 8 kB sector erase (40h) command will not work on a 64 kB sector." Referring further to Table 8.1 and Table 8.2, it is clearly seen that most of the sectors are 64KiB; therefore disable this 4KiB erase support since it's valid only on first/last sectors. Signed-off-by:
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Rafał Miłecki authored
This registers MTD driver for serial flash platform device. Right now it supports reading only, writing still has to be implemented. Artem: minor amendments. Signed-off-by:
Rafał Miłecki <zajec5@gmail.com> Signed-off-by:
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David Woodhouse authored
Merge commit '371a0044' of 'git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next.git' We need the following 2 patches from the 'net-next' tree for the BCMA flash driver: 371a0044 bcma: detect and register NAND flash device d57ef3a6 bcma: detect and register serial flash device and this is why we are merging the net-next tree (presumably persistent) up to commit '371a0044'. Signed-off-by:
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Akinobu Mita authored
Currently the data blocks which is used to test single bit error correction is allocated statically and injecting single bit error is implemented by using __change_bit() which must operate on the memory aligned to the size of an "unsigned long". But there is no such guarantee for statically allocated array. This fix the issue by allocating the data block dynamically by kmalloc(). It also allocate the ecc code dynamically instead of allocating statically on stack. The reason to allocate the ecc code dynamically is that later change will add tests which inject bit errors into the ecc code by bitops. Signed-off-by:
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Akinobu Mita authored
This includes the message related changes: - Use pr_* instead of printk - Print hexdump of ECC code if test fails - Change log level for hexdump of data from KERN_DEBUG to KERN_INFO - Factor out the hexdump code into a separate function Signed-off-by:
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Akinobu Mita authored
Return -EINVAL instead of -1 (-EPERM) when test fails. Signed-off-by:
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Akinobu Mita authored
Including linux/jiffies.h was required for calling srandom32(jiffies) that has already been removed. Signed-off-by:
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Brian Norris authored
JFFS2 was designed without thought for OOB bitflips, it seems, but they can occur and will be reported to JFFS2 via mtd_read_oob()[1]. We don't want to fail on these transactions, since the data was corrected. [1] Few drivers report bitflips for OOB-only transactions. With such drivers, this patch should have no effect. Signed-off-by: -
Julia Lawall authored
devm free functions should not have to be explicitly used. Signed-off-by:
Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by:
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