- 12 Aug, 2023 7 commits
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Arnd Bergmann authored
Merge tag 'microchip-dt64-6.6' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into soc/dt Microchip ARM64 device tree updates for 6.6 It contains: - one cleanup patch that removes whitespaces around '=' * tag 'microchip-dt64-6.6' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux: arm64: dts: microchip: minor whitespace cleanup around '=' Link: https://lore.kernel.org/r/20230804044132.231508-1-claudiu.beznea@tuxon.devSigned-off-by: Arnd Bergmann <arnd@arndb.de>
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https://git.kernel.org/pub/scm/linux/kernel/git/at91/linuxArnd Bergmann authored
AT91 device tree updates for 6.6 It contains: - TCB timer nodes adition for at91-sama5d3_ksz9477_evb board - device tee cleanups * tag 'at91-dt-6.6' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux: ARM: dts: at91: remove duplicated entries ARM: dts: microchip: split interrupts per cells ARM: dts: at91: ksz9477_evb: Add tx-internal-delay-ps property for port5 ARM: dts: at91: ksz9477_evb: Add missing timer nodes ARM: dts: at91-vinco: Fix "status" values ARM: dts: microchip: add missing space before { ARM: dts: microchip: minor whitespace cleanup around '=' Link: https://lore.kernel.org/r/20230804044102.231448-1-claudiu.beznea@tuxon.devSigned-off-by: Arnd Bergmann <arnd@arndb.de>
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Krzysztof Kozlowski authored
Each interrupt should be in its own cell. This is much more readable. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Link: https://lore.kernel.org/r/20230730111536.98164-1-krzysztof.kozlowski@linaro.orgSigned-off-by: Arnd Bergmann <arnd@arndb.de>
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Arnd Bergmann authored
Merge tag 'renesas-dts-for-v6.6-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt Renesas DTS updates for v6.6 - Add Clocked Serial Interface (CSI) support for the RZ/V2M SoC, - Add PMIC, RTC, and PWM support for the RZ/G2L, RZ/G2LC, and RZ/V2L SMARC EVK development boards, - Add PWM (MTU3a) support for the RZ/G2UL and RZ/Five SoCs, - Add External interrupt (INTC-EX) support for the R-Car S4-8 SoC, - Add LED support for the Spider development board, - Miscellaneous fixes and improvements. * tag 'renesas-dts-for-v6.6-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: arm64: dts: renesas: spider-cpu: Add GP LEDs arm64: dts: renesas: r8a779f0: Add INTC-EX node arm64: dts: renesas: rzg2ul-smarc: Add support for enabling MTU3 arm64: dts: renesas: r9a07g043: Add MTU3a node ARM dts: renesas: armadillo800eva: Switch to enable-gpios arm64: dts: renesas: rzg2lc-smarc-som: Enable PMIC and built-in RTC arm64: dts: renesas: rzg2lc-smarc-som: Add PHY interrupt support for ETH0 riscv: dts: renesas: Clean up dtbs_check W=1 warning due to empty phy node arm64: dts: renesas: rzg2lc-smarc: Add support for enabling MTU3 arm64: dts: renesas: rzg2l-smarc: Add support for enabling MTU3 arm64: dts: renesas: Add missing space before { ARM: dts: renesas: Add missing space before { arm64: dts: renesas: Minor whitespace cleanup around '=' arm64: dts: renesas: rzg2l-smarc-som: Enable PMIC and built-in RTC arm64: dts: renesas: r9a09g011: Add CSI nodes arm64: dts: renesas: rzg2l: Fix txdv-skew-psec typos arm64: dts: renesas: rzg2l: Update overfow/underflow IRQ names for MTU3 channels Link: https://lore.kernel.org/r/cover.1690545144.git.geert+renesas@glider.beSigned-off-by: Arnd Bergmann <arnd@arndb.de>
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Arnd Bergmann authored
Merge tag 'tegra-for-6.6-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt arm64: tegra: Device tree changes for v6.6-rc1 The majority of this is fixes all over the place for DT schema validation warnings. However, there are also cleanups for some things in DT and audio support is added on IGX Orin. Jetson Orin NX and Nano also gain a new thermal trip point to help keep the device cool at moderate loads. * tag 'tegra-for-6.6-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: (22 commits) arm64: tegra: Add blank lines for better readability arm64: tegra: Remove {clock,reset}-names from VIC powergate arm64: tegra: Drop incorrect maxim,disable-etr on Smaug arm64: tegra: Add SPI device tree nodes for Tegra234 arm64: tegra: Enable UARTA and UARTE for Orin Nano arm64: tegra: Add UARTE device tree node on Tegra234 arm64: tegra: Adapt to LP855X bindings changes arm64: tegra: Add PCIe and DP 3.3V supplies arm64: tegra: Add missing reset-names for Tegra HS UART arm64: tegra: Remove current-speed for SBSA UART arm64: tegra: smaug: Remove reg-shift for high-speed UART arm64: tegra: Remove dmas and dma-names for debug UART arm64: tegra: Add 35°C trip point for Jetson Orin NX/Nano arm64: tegra: Remove duplicate PCI nodes arm64: tegra: Sort PCI nodes correctly on Orin arm64: tegra: Add audio support for IGX Orin arm64: tegra: Update CPU OPP tables arm64: tegra: Fix HSUART for Smaug arm64: tegra: Fix HSUART for Jetson AGX Orin arm64: tegra: Add missing alias for NVIDIA IGX Orin ... Link: https://lore.kernel.org/r/20230728094129.3587109-4-thierry.reding@gmail.comSigned-off-by: Arnd Bergmann <arnd@arndb.de>
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Arnd Bergmann authored
Merge tag 'tegra-for-6.6-arm-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt ARM: tegra: Device tree changes for v6.6-rc1 This contains various fixes for DT schema validation and the Pegatron Chagall and Nexus 7 get specific compatible strings for the panels that they use. * tag 'tegra-for-6.6-arm-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: ARM: tegra: Provide specific compatible string for Nexus 7 panel ARM: tegra: Use Hannstar HSD101PWW2 on Pegatron Chagall ARM: tegra: Reuse I2C3 for NVEC ARM: tegra: Add missing reset-names for Tegra HS UART ARM: tegra: Remove reset-names for UART devices ARM: tegra: Remove dmas and dma-names for debug UART Link: https://lore.kernel.org/r/20230728094129.3587109-3-thierry.reding@gmail.comSigned-off-by: Arnd Bergmann <arnd@arndb.de>
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Arnd Bergmann authored
Merge tag 'tegra-for-6.6-dt-bindings' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt dt-bindings: Changes for v6.6-rc1 A number of Tegra-specific bindings are converted to json-schema and the reserved-memory and BPMP bindings get support for Tegra264. * tag 'tegra-for-6.6-dt-bindings' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: dt-bindings: firmware: Add support for tegra186-bpmp DRAM MRQ GSCs dt-bindings: reserved-memory: Add support for DRAM MRQ GSCs dt-bindings: thermal: tegra: Convert to json-schema dt-bindings: arm: tegra: nvec: Convert to json-schema dt-bindings: clock: tegra: Document Tegra132 compatible dt-bindings: cpu: Document NVIDIA Tegra186 CCPLEX cluster dt-bindings: serial: tegra-hsuart: Convert to json-schema dt-bindings: arm: tegra: ahb: Convert to json-schema dt-bindings: arm: tegra: flowctrl: Convert to json-schema Link: https://lore.kernel.org/r/20230728094129.3587109-2-thierry.reding@gmail.comSigned-off-by: Arnd Bergmann <arnd@arndb.de>
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- 04 Aug, 2023 1 commit
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Claudiu Beznea authored
Remove duplicated DTC_FLAGS_<board> := -@ entries which intends to enable the building of device tree overlays. Commit 724ba675 ("ARM: dts: Move .dts files to vendor sub-directories") added those entries at the beginning of file w/o removing the already available entries spread though file. Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20230721053918.33944-1-claudiu.beznea@tuxon.devSigned-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
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- 02 Aug, 2023 1 commit
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Krzysztof Kozlowski authored
Each interrupt should be in its own cell. This is much more readable. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20230730111542.98238-1-krzysztof.kozlowski@linaro.orgSigned-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
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- 31 Jul, 2023 3 commits
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Lukasz Majewski authored
Without this change the KSZ9477 Evaluation board's Linux (v6.5-rc1) shows following device warning: 'ksz-switch spi1.0: Port 5 interpreting RGMII delay settings based on "phy-mode" property, please update device tree to specify "rx-internal-delay-ps" and "tx-internal-delay-ps"' This is not critical, as KSZ driver by itself assigns default value of tx delay to 2000 ps (as 'rgmii-txid' is set as PHY mode). However, to avoid extra warnings in logs - the missing 'tx-internal-delay-ps' has been specified with the default value of 2000 ps. Signed-off-by: Lukasz Majewski <lukma@denx.de> Link: https://lore.kernel.org/r/20230727080656.3828397-1-lukma@denx.deSigned-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
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Lukasz Majewski authored
Without this change the KSZ9477-EVB board hangs just after passing execution flow from u-boot to Linux kernel. This code has been copied from at91-sama5d3_xplained.dts. Test setup: Linux 6.5-rc1 Config: arch/arm/configs/sama5_defconfig Toolchain: gcc-linaro-7.3.1-2018.05-x86_64_arm-linux-gnueabi Signed-off-by: Lukasz Majewski <lukma@denx.de> Link: https://lore.kernel.org/r/20230712152111.3756211-1-lukma@denx.deSigned-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
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Rob Herring authored
The defined value for "status" is "disabled", not "disable". Signed-off-by: Rob Herring <robh@kernel.org> Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20230626221010.3946263-1-robh@kernel.orgSigned-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
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- 29 Jul, 2023 3 commits
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Krzysztof Kozlowski authored
The DTS code coding style expects exactly one space before and after '=' sign. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Steen Hegelund <Steen.Hegelund@microchip.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20230702185108.43959-1-krzysztof.kozlowski@linaro.org [claudiu.beznea: added link] Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
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Krzysztof Kozlowski authored
Add missing whitespace between node name/label and opening {. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20230705150058.293942-1-krzysztof.kozlowski@linaro.org [claudiu.beznea: added link] Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
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Krzysztof Kozlowski authored
The DTS code coding style expects exactly one space before and after '=' sign. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Steen Hegelund <Steen.Hegelund@microchip.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20230702185108.43959-1-krzysztof.kozlowski@linaro.org [claudiu.beznea: added link] Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
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- 27 Jul, 2023 14 commits
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Thierry Reding authored
panel-lvds alone is not a valid compatible string and we always need a specific compatible string as well. Nexus 7 can come with one of (at least) two panels, so pick one of them as the specific compatible string. Signed-off-by: Thierry Reding <treding@nvidia.com>
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Thierry Reding authored
The LVDS bindings require a specific compatible string in addition to the generic "panel-lvds". Add the HannStar HSD101PWW2 which is used on a similar device (ASUS TF201) and seems to work fine with slightly modified timings in DT. Suggested-by: Svyatoslav Ryhel <clamor95@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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Thierry Reding authored
Instead of duplicating the I2C3 node and adding NVEC specific properties, reuse the I2C3 node, extend it with NVEC specific properties and drop properties that are not needed by NVEC. This results in a DTB that is a bit cleaner and avoids accidentally using I2C3 and NVEC which would have them fight over the same hardware resources. Signed-off-by: Thierry Reding <treding@nvidia.com>
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Thierry Reding authored
Add a few blank lines to visually separate blocks in the Jetson AGX Orin device tree. Signed-off-by: Thierry Reding <treding@nvidia.com>
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Thierry Reding authored
According to the device tree bindings, the powergate definition nodes don't contain clock-names and reset-names properties, so remove them. Signed-off-by: Thierry Reding <treding@nvidia.com>
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Krzysztof Kozlowski authored
There is no "maxim,disable-etr" property (but there is maxim,enable-etr), neither in the bindings nor in the Linux driver: tegra210-smaug.dtb: regulator@1c: Unevaluated properties are not allowed ('maxim,disable-etr' was unexpected) Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Diogo Ivo <diogo.ivo@tecnico.ulisboa.pt> Signed-off-by: Thierry Reding <treding@nvidia.com>
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Gautham Srinivasan authored
Create the device tree nodes for the SPI1, SPI2 and SPI3 controllers found on Tegra234. Signed-off-by: Gautham Srinivasan <gauthams@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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Gautham Srinivasan authored
Activate UARTA and UARTE functionalities for Orin Nano. - UARTA is accessible via the 40-pin header with pin 8 and 10 (TX/RX) - UARTE utilizes the M2.E connector Signed-off-by: Gautham Srinivasan <gauthams@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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Gautham Srinivasan authored
This commit adds the device tree node for UARTE on Tegra234. Signed-off-by: Gautham Srinivasan <gauthams@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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Geert Uytterhoeven authored
Describe the two General Purpose LEDs LED7 and LED8 on the Spider CPU board, so they can be used as indicator LEDs. Note that General Purpose LEDs LED9 to LED11 are not added, as they are connected to GPIO block 4, which can only be accessed from the Control Domain. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/fdaf6c700b624851039a60733c7f73a413c6d2c5.1690447094.git.geert+renesas@glider.be
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Geert Uytterhoeven authored
Add the device node for the Interrupt Controller for External Devices (INTC-EX) on the Renesas R-Car S4-8 (R8A779F0) SoC, which serves external IRQ pins IRQ[0-5]. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/8f5612c0353b8c90f98366978563340d93c7ae58.1690447013.git.geert+renesas@glider.be
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Biju Das authored
Add support for PMOD_MTU3 macro to enable MTU3 node on RZ/G2UL SMARC EVK. The MTU3a PWM pins on PMOD0 are muxed with SPI1. Disable SPI1, when PMOD_MTU3 macro is enabled. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230727081848.100834-6-biju.das.jz@bp.renesas.comSigned-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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Biju Das authored
Add MTU3a node to R9A07G043 (RZ/{G2UL,Five}) SoC DTSI. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230727081848.100834-5-biju.das.jz@bp.renesas.comSigned-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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Krzysztof Kozlowski authored
The recommended name for enable GPIOs property in regulator-gpio is "enable-gpios". This is also required by bindings: r8a7740-armadillo800eva.dtb: regulator-vccq-sdhi0: Unevaluated properties are not allowed ('enable-gpio' was unexpected) Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230726070241.103545-1-krzysztof.kozlowski@linaro.orgSigned-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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- 26 Jul, 2023 11 commits
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Artur Weber authored
Change underscores in ROM node names to dashes, and remove deprecated pwm-period property. Signed-off-by: Artur Weber <aweber.kernel@gmail.com> Reviewed-by: Daniel Thompson <daniel.thompson@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
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Shubhi Garg authored
Add the 3.3V supplies for PCIe C1 controller and Display Port controller for the NVIDIA IGX Orin platform. Signed-off-by: Shubhi Garg <shgarg@nvidia.com> Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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Thierry Reding authored
The device tree bindings for the Tegra high-speed UART require the reset-names property, so add it whenever the compatible string for the serial port is overwritten. Signed-off-by: Thierry Reding <treding@nvidia.com>
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Thierry Reding authored
The SBSA UART device tree bindings don't define a current-speed property, so remove it. Signed-off-by: Thierry Reding <treding@nvidia.com>
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Thierry Reding authored
The device tree bindings for the high-speed UART don't define a reg-shift property, so delete it. Signed-off-by: Thierry Reding <treding@nvidia.com>
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Thierry Reding authored
The debug UART doesn't support DMA and the DT bindings prohibit the use of the dmas and dma-names properties for it, so remove them. Signed-off-by: Thierry Reding <treding@nvidia.com>
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Thierry Reding authored
It turns out that these devices can get quite hot to the touch with the standard cooling configuration, so add another trip point at 35°C along with a cooling map to help keep the system reasonably cool at very low system load. Reviewed-by: Yi-Wei Wang <yiweiw@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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Thierry Reding authored
The PCI nodes for Jetson Orin NX are already defined at the carrier board level, so the duplicates can be dropped at the platform level. Signed-off-by: Thierry Reding <treding@nvidia.com>
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Thierry Reding authored
Recent changes to several Orin boards didn't order some device tree nodes correctly. Resort them. Signed-off-by: Thierry Reding <treding@nvidia.com>
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Mohan Kumar authored
Add audio support for the NVIDIA IGX Orin development kit having P3701 module with P3740 carrier board. Move the common device-tree nodes to a new file tegra234-p3701.dtsi and use this for Jetson AGX Orin and NVIDIA IGX Orin platforms Signed-off-by: Mohan Kumar <mkumard@nvidia.com> [treding@nvidia.com: properly sort nodes] Signed-off-by: Thierry Reding <treding@nvidia.com>
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Peter De Schrijver authored
Add memory-region property to the tegra186-bpmp binding to support DRAM MRQ GSCs. Co-developed-by: Stefan Kristiansson <stefank@nvidia.com> Signed-off-by: Stefan Kristiansson <stefank@nvidia.com> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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