- 15 Sep, 2021 40 commits
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Michael Riesch authored
Add the SARADC to the device tree of the RK3568 EVB1. Signed-off-by:
Michael Riesch <michael.riesch@wolfvision.net> Link: https://lore.kernel.org/r/20210823110716.10038-1-michael.riesch@wolfvision.netSigned-off-by:
Heiko Stuebner <heiko@sntech.de>
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Alex Bee authored
As can be seen in RK3328's TRM the register range for the GPU is 0xff300000 to 0xff330000. It would (and does in vendor kernel) overlap with the registers of the HEVC encoder (node/driver do not exist yet in upstream kernel). See already existing h265e_mmu node. Fixes: 752fbc0c ("arm64: dts: rockchip: add rk3328 mali gpu node") Signed-off-by:
Alex Bee <knaerzche@gmail.com> Link: https://lore.kernel.org/r/20210623115926.164861-1-knaerzche@gmail.comSigned-off-by:
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Alex Bee authored
Commit 53a05c8f6e8e ("arm64: dts: rockchip: remove interrupt-names from iommu nodes") intended to remove the interrupt-names property for mmu nodes, but it also removed it for the vpu node in rk3399.dtsi. That makes the driver fail probing currently. Fix this by re-adding the property for this node. Fixes: 53a05c8f6e8e ("arm64: dts: rockchip: remove interrupt-names from iommu nodes") Signed-off-by: -
Michael Riesch authored
This commit fixes the error messages rockchip_clk_register_muxgrf: regmap not available rockchip_clk_register_branches: failed to register clock clk_ddr1x: -524 during boot by providing the missing rockchip,grf property. Signed-off-by:
Peter Geis <pgwipeout@gmail.com> Link: https://lore.kernel.org/r/20210823123911.12095-2-michael.riesch@wolfvision.netSigned-off-by:
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Brian Norris authored
It's convenient to get nice names for GPIOs. In particular, Chrome OS tooling looks for "AP_FLASH_WP" and "AP_FLASH_WP_L". The rest are provided for convenience. Gru-Bob and Gru-Kevin share the gru-chromebook.dtsi, and for the most part they share pin meanings. I omitted a few areas where components were available only on one or the other. Signed-off-by:
Brian Norris <briannorris@chromium.org> Reviewed-by:
Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20210820133829.1.Ica46f428de8c3beb600760dbcd63cf879ec24baf@changeidSigned-off-by:
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Chris Morgan authored
This enables the Rockchip Serial Flash Controller for the Odroid Go Advance. Note that while the attached SPI NOR flash and the controller both support quad read mode, only 2 of the required 4 pins are present. The rx bus width is set to 2 for this reason, and tx bus width is set to 1 for compatibility reasons. Signed-off-by:
Chris Morgan <macromorgan@hotmail.com> Signed-off-by:
Jon Lin <jon.lin@rock-chips.com> Link: https://lore.kernel.org/r/20210812134639.31586-2-jon.lin@rock-chips.comSigned-off-by:
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Chris Morgan authored
Add a devicetree entry for the Rockchip SFC for the RK3308 SOC. Signed-off-by:
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Chris Morgan authored
Add a devicetree entry for the Rockchip SFC for the PX30 SOC. Signed-off-by:
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Peter Geis authored
Add the thermal nodes for the Quartz64 Model A. The Model A supports a single speed gpio fan. Signed-off-by:
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Peter Geis authored
Add the thermal and tsadc nodes to the rk3568 device tree. There are two sensors, one for the cpu, one for the gpu. Signed-off-by:
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Peter Geis authored
The rk356x added a debounce clock to the gpio devices. This clock is necessary for the new v2 gpio driver to bind. Add the clocks to the rk356x device tree. Signed-off-by:
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Michael Riesch authored
Since the EMMC pins can be used for other functions as well, we need to configure the pinctrl. Signed-off-by:
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Michael Riesch authored
Add the SD card reader to the device tree of the RK3568 EVB1. Signed-off-by:
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Michael Riesch authored
Add the regulators of the RK809 PMIC to the device tree of the RK3568 EVB1. Signed-off-by:
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Michael Riesch authored
Enable the PMU IO domains in the device tree for the RK3568 EVB1. Signed-off-by:
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Michael Riesch authored
Enable the PMU IO domains for the RK3566 and the RK3568. Signed-off-by:
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Peter Geis authored
The rockpro64 had a fan node since commit 5882d65c ("arm64: dts: rockchip: Add PWM fan for RockPro64") however it was never tied into the thermal driver for automatic control. Add the links to the thermal node to permit the kernel to handle this automatically. Borrowed from the (rk3399-khadas-edge.dtsi). Signed-off-by:
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Dan Johansen authored
Some chargers try to put the charged device into device data role. Before this commit this condition caused the tcpm state machine to issue a hard reset due to a capability missmatch. Signed-off-by:
Dan Johansen <strit@manjaro.org> Link: https://lore.kernel.org/r/20210805220426.2693062-1-strit@manjaro.orgSigned-off-by:
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Chen-Yu Tsai authored
Dumo is another variant of Scarlet, also known as the ASUS Chromebook Tablet CT100. This is almost the same as Scarlet-Innolux, but uses a board-specific calibration variant for the WiFi module. Add a new device tree for it. Signed-off-by:
Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20210812094753.2359087-3-wenst@chromium.orgSigned-off-by:
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Chen-Yu Tsai authored
Dumo is another variant of Scarlet, also known as the ASUS Chromebook Tablet CT100. This is almost the same as Scarlet-Innolux, but uses a specific calibration variant for the WiFi module. Add an entry for the board compatibles. Signed-off-by:
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Michael Riesch authored
Signed-off-by:
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Michael Riesch authored
While both RK3566 and RK3568 feature the gmac1 node, the gmac0 node is exclusive to the RK3568. Signed-off-by:
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Peter Geis authored
Enable the gmac controller on the Pine64 Quartz64 Model A. Signed-off-by:
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Peter Geis authored
The rk3568 gpll should run at 1200mhz and the ppll should run at 200mhz. These are set incorrectly by the bootloader, so fix them here. gpll boots at 1188mhz, but to get most accurate dividers for all gpll_dividers it needs to run at 1200mhz, otherwise everyone downstream isn't quite right. ppll feeds the combophys, which has a divide by 2 clock, so 200mhz is required to reach a 100mhz clock input for them. The vendor-kernel also makes this fix. Signed-off-by:
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Peter Geis authored
Add the gmac1 controller to the rk356x device tree. This is the controller common to both the rk3568 and rk3566. Signed-off-by:
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Peter Geis authored
The mbi-alias incorrectly points to 0xfd100000 when it should point to 0xfd410000. This fixes MSIs on rk3568. Fixes: a3adc0b9 ("arm64: dts: rockchip: add core dtsi for RK3568 SoC") Signed-off-by:
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Paul Kocialkowski authored
The PX30 has a VPU (both decoder and encoder) with a dedicated IOMMU. Describe these two entities in device-tree. Signed-off-by:
Paul Kocialkowski <paul.kocialkowski@bootlin.com> Signed-off-by:
Ezequiel Garcia <ezequiel@collabora.com> Link: https://lore.kernel.org/r/20210728230040.17368-1-ezequiel@collabora.comSigned-off-by:
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Liang Chen authored
Add the watchdog node to rk3568. Signed-off-by:
Liang Chen <cl@rock-chips.com> Signed-off-by:
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Heiko Stuebner authored
ISP1 is supplied by the tx1rx1 dphy, that is controlled from inside the dsi1 controller, so include the necessary phy-link for it. Signed-off-by:
Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Tested-by:
Sebastian Fricke <sebastian.fricke@posteo.net> Acked-by:
Helen Koike <helen.koike@collabora.com> Link: https://lore.kernel.org/r/20210210111020.2476369-7-heiko@sntech.deSigned-off-by:
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Heiko Stuebner authored
This enables variant a of the clkout signal for camera applications and also the cifclkin pinctrl setting. Signed-off-by:
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Heiko Stuebner authored
The dsi controller includes access to the dphy which might be used not only for dsi output but also for csi input on dsi1, so add the necessary #phy-cells to allow it to be used as phy. Signed-off-by:
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Peter Geis authored
Add a basic dts for the Pine64 Quartz64 Model A Single Board Computer. This board outputs on uart2 for debug. Signed-off-by:
Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20210710151034.32857-5-pgwipeout@gmail.comSigned-off-by:
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Peter Geis authored
Add the rk3566 dtsi which includes the soc specific changes for this chip. Signed-off-by:
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Peter Geis authored
In preparation for the rk3566 inclusion, split apart the rk3568 specific nodes into a separate device tree. This allows us to create the rk3566 device tree without deleting nodes. Signed-off-by:
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Peter Geis authored
In preparation for separating the rk3568 and rk3566 device trees, move the base rk3568 dtsi to rk356x dtsi. This will allow us to strip out the rk3568 specific nodes. Signed-off-by:
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Heiko Stuebner authored
Add the CSI dphy node to the core px30 devicetree for later use with the rkisp. Signed-off-by:
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Alex Bee authored
Add a SPDIF audio-graph-card to ROCK Pi 4 device tree. It's not enabled by default since all dma channels are used by the (already) enabled i2s0/1/2 and the pin is muxed with GPIO4_C5 which might be in use already. If enabled SPDIF_TX will be available at pin #15. Signed-off-by:
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Alex Bee authored
ROCK Pi 4 boards have the codec connected to i2s0 and it is accessible via i2c1 address 0x11. Add an audio-graph-card for it. Signed-off-by:
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Alex Bee authored
ROCK Pi 4B+ board is the successor of ROCK Pi 4B board. Differences to the original version are - has RK3399 OP1 SoC revision - has eMMC (16 or 32 GB) soldered on board (no changes required, since it is enabled in rk3399-rock-pi-4.dtsi) - dev boards have SPI flash soldered, but as per manufacturer response, this won't be the case for mass production boards Signed-off-by:
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Alex Bee authored
ROCK Pi 4A+ board is the successor of ROCK Pi 4A board. Differences to the original version are - has RK3399 OP1 SoC revision - has eMMC (16 or 32 GB) soldered on board (no changes required, since it is enabled in rk3399-rock-pi-4.dtsi) - dev boards have SPI flash soldered, but as per manufacturer response, this won't be the case for mass production boards Signed-off-by:
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