Increase the number of interconnect-cells, as now we can include
the tag information. The consumers can specify the path tag as an
additional argument to the endpoints.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Tested-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
Link: https://lore.kernel.org/r/20200903133134.17201-8-georgi.djakov@linaro.orgSigned-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

Increase the number of interconnect-cells, as now we can include
the tag information. The consumers can specify the path tag as an
additional argument to the endpoints.
Tested-by: Sibi Sankar <sibis@codeaurora.org>
Reviewed-by: Sibi Sankar <sibis@codeaurora.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
Link: https://lore.kernel.org/r/20200903133134.17201-6-georgi.djakov@linaro.orgSigned-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

The Makefile is in a bit of a weird order at the moment.
It's almost sorted alphabetically, but not entirely.
Also, one element uses a space before the += instead of a tab.

Fix this up and sort the lines alphabetically so we have
a consistent order in the Makefile.
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20200915071221.72895-15-stephan@gerhold.netSigned-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

Sort nodes by unit address so we have a consistent order in pm8916.dtsi.
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20200915071221.72895-14-stephan@gerhold.netSigned-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

Just like in commit 50aa72cc ("arm64: dts: qcom: msm8996:
Sort all nodes in msm8996.dtsi"), sort all the nodes by unit address,
then alphabetically by their name.
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20200915071221.72895-13-stephan@gerhold.netSigned-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

Just like in commit 86f6d622 ("arm64: dts: qcom: msm8996: Pad addresses"),
pad all addresses to 8 digits to make it easier to see the correct
order of the nodes.
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20200915071221.72895-12-stephan@gerhold.netSigned-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

This allows grouping them together when sorting nodes alphabetically.
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20200915071221.72895-11-stephan@gerhold.netSigned-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

Now that all MSM8916 boards are referencing nodes by label instead
of name, we can easily make some more nodes use more generic names
(as recommended in the device tree specification or the binding
documentation).
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20200915071221.72895-10-stephan@gerhold.netSigned-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

Over the time, the SCM and MSS driver were refactored to use
SoC-specific compatibles. While the generic compatibles still work
correctly, add the MSM8916-specific compatibles so they are actually
used somewhere.

For SCM this will ensure that we actually manage to obtain all
three of the specified clocks, since those are required on MSM8916.
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20200915071221.72895-9-stephan@gerhold.netSigned-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

Fix usages of spaces for indentation, break a long line
and remove duplicate new lines. Add some spaces where appropriate.
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20200915071221.72895-8-stephan@gerhold.netSigned-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

The hwlock device node does not (directly) use memory resources
of the SoC, so we should move it outside the "soc" node.

However, as of commit 7a1e6fb1 ("hwspinlock: qcom: Allow mmio usage
in addition to syscon") we can now assign the memory region directly
to the hwlock device node. This works because the register space
used by it is actually separate and not used by any other components.
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20200915071221.72895-7-stephan@gerhold.netSigned-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

dt-bindings/interrupt-controller/arm-gic.h has a GIC_SPI define
that allows specifying interrupts more clearly, but right now only
some device nodes in msm8916.dtsi make use of it.
Convert all others to use it.

The same applies to the IRQ_TYPE_* defines in
dt-bindings/interrupt-controller/irq.h. Some interrupts were defined
with raw numbers, or even with IRQ_TYPE_NONE (0).
Convert all these to use appropriate IRQ types.
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20200915071221.72895-6-stephan@gerhold.netSigned-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

The mdss node sets #interrupt-cells = <1>, so its interrupts
should be referenced using a single cell (in this case: only the
interrupt number).

However, right now the mdp/dsi node both have two interrupt cells
set, e.g. interrupts = <4 0>. The 0 is probably meant to say
IRQ_TYPE_NONE (= 0), but with #interrupt-cells = <1> this is
actually interpreted as a second interrupt line.

Remove the IRQ flags from both interrupts to fix this.

Fixes: 305410ff ("arm64: dts: msm8916: Add display support")
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20200915071221.72895-5-stephan@gerhold.netSigned-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

Tha parent node of "wcd_codec" specifies #address-cells = <1>
and #size-cells = <0>, which means that each resource should be
described by one cell for the address and size omitted.

However, wcd_codec currently lists 0x200 as second cell (probably
the size of the resource). When parsing this would be treated like
another memory resource - which is entirely wrong.

To quote the device tree specification [1]:
  "If the parent node specifies a value of 0 for #size-cells,
   the length field in the value of reg shall be omitted."

[1]: https://www.devicetree.org/specifications/

Fixes: 5582fcb3 ("arm64: dts: apq8016-sbc: add analog audio support with multicodec")
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20200915071221.72895-4-stephan@gerhold.netSigned-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

Commit fe2aff0c ("arm64: dts: qcom: msm8916: remove unit name for thermal trip points")
removed the unit names for most of the thermal trip points defined
in msm8916.dtsi, but missed to update the one for cpu0_1-thermal.

So why wasn't this spotted by "make dtbs_check"? Apparently, the name
of the thermal zone is already invalid: thermal-zones.yaml specifies
a regex of ^[a-zA-Z][a-zA-Z0-9\\-]{1,12}-thermal$, so it is not allowed
to contain underscores. Therefore the thermal zone was never verified
using the DTB schema.

After replacing the underscore in the thermal zone name, the warning
shows up:

    apq8016-sbc.dt.yaml: thermal-zones: cpu0-1-thermal:trips: 'trip-point@0'
    does not match any of the regexes: '^[a-zA-Z][a-zA-Z0-9\\-_]{0,63}$', 'pinctrl-[0-9]+'

Fix up the thermal zone names and remove the unit name for the trip point.

Cc: Amit Kucheria <amit.kucheria@linaro.org>
Fixes: fe2aff0c ("arm64: dts: qcom: msm8916: remove unit name for thermal trip points")
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20200915071221.72895-3-stephan@gerhold.netSigned-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

&dsi0 -> ports -> port@1 -> endpoint already has the "dsi0_out" label,
so we can use it for configuring instead of replicating the entire
node hierarchy. Looks like I missed that when converting the boards.
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20200915071221.72895-2-stephan@gerhold.netSigned-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

qup has a requirement to vote on the performance state of the CX domain
in sm8250 devices. Add OPP tables for these and also add power-domains
property for all qup instances for uart and spi.
i2c does not support scaling and uses a fixed clock.
Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20200915120203.290295-1-dmitry.baryshkov@linaro.orgSigned-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

As the MSM8996 has two VFE IP-blocks, and each has a power domain,
both of them have to be enabled. Previously only the power domain
of VFE0 was enabled, but not the domain for VFE1.

This patch adds the VFE1_GDSC power domain to the camss device tree
node of the MSM8996 soc.
Signed-off-by: Robert Foss <robert.foss@linaro.org>
Link: https://lore.kernel.org/r/20200915142316.147208-1-robert.foss@linaro.orgSigned-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

Right now we define "hnp-disable", "srp-disable", "adp-disable"
separately for every MSM8916 board that has USB working.

They are needed for USB to work properly if CONFIG_USB_OTG_FSM
is enabled. This is because the chipidea OTG FSM code waits for
interrupts regarding the VBUS state (AVVIS). Those never happen
on MSM8916 because VBUS is always connected to the PMIC instead
of the USB controller.

There was a patch [1] to work around this but ultimately it was
decided that it's easier to disable the OTG FSM altogether using
these properties. This works fine for most use cases, because the
OTG FSM isn't needed for simple dual role host/gadget operation.

Given that these properties are needed for every MSM8916 device,
move them to msm8916.dtsi so we can avoid some more duplication.

[1]: https://lore.kernel.org/lkml/20160707222114.1673-10-stephen.boyd@linaro.org/Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20200720085406.6716-11-stephan@gerhold.netSigned-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

Right now some device nodes set default pinctrl within msm8916.dtsi
(e.g. I2C, SPI), but for others it needs to be explicitly set in the
board-specific device tree (e.g. UART).

While it is theoretically possible that some super special board
needs different pinctrl for these, in practice pretty much every
board ends up using the common pinctrl definitions.

Make this consistent by also defining the common pinctrl properties
for blsp1_uart1 and blsp1_uart2 so we don't need to copy this for every
board. If there is really such a super special board it could just
override these properties with custom pinctrl or make minor modifications
to the common pinctrl configurations provided by msm8916-pins.dtsi.

Also move #address-cells/#size-cells for &dsi0 to msm8916.dtsi
since this is specific to the DSI node, not the board.
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20200720085406.6716-10-stephan@gerhold.netSigned-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

So far we had some supplies defined for all boards in msm8916.dtsi,
while others were duplicated into every board-specific device tree.

Now that we have msm8916-pm8916.dtsi as a common include for all
standard MSM8916 devices using PM8916, move the remaining common
supplies to msm8916-pm8916.dtsi to reduce duplication a bit.
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20200720085406.6716-9-stephan@gerhold.netSigned-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

Device trees for newer SoCs avoid defining the regulator nodes directly
in the SoC device tree (here: msm8916.dtsi). The reason for this is that
theoretically it is possible to combine the SoC with a different PMIC,
or to use all the regulators in a board-specific way.

Therefore let's remove those from the SoC include (msm8916.dtsi).

In practice, pretty much all MSM8916 boards were combined with PM8916,
and use the regulators in similar ways. After looking at many different
MSM8916 boards (mostly smartphones and tablets), I haven't seen a single
device that isn't using the same regulators for components integrated
into the SoC.

If all boards end up defining all regulators and supplies in the same way
then it is useful to have an include for that, so we can avoid duplicating
it everywhere. If there is really a super special board that does it
differently it could just override some properties or avoid using the
include altogether.

This patch moves the regulator and common supply definitions to
a new include called "msm8916-pm8916.dtsi".

This is also going to be useful when introducing CPR (Core Power
Reduction) later because we can configure the CPU regulator
(pm8916_spmi_s2) for all devices in this common include.
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20200720085406.6716-8-stephan@gerhold.netSigned-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

Right now we define the entire pm8916 resin node separately in
the board-specific device tree part, including the interrupt that
belongs to PM8916.

As a feature of the PMIC it should be declared in pm8916.dtsi,
disabled by default. Like all other optional components it can then
by enabled and configured in the board-specific device tree part.
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20200720085406.6716-7-stephan@gerhold.netSigned-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

Device trees for newer SoCs avoid replicating the entire device
hierarchy in the board-specific device tree part. Instead,
they set additional properties only by referencing labels,
sorted alphabetically.

Now that we have labels for all relevant nodes, convert the MSM8916
board device trees to use the same style and remove the "soc" node
entirely.

Note: There is a large block of coresight nodes in apq8016-sbc.dtsi,
which are enabled by setting status = "okay". I kept them grouped
together (not alphabetically sorted with everything else),
since that would be just unnecessarily verbose and hard to see.

This commit only moves all existing properties to nodes that reference
the respective label. The resulting binary DTBs are exactly the same.
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20200720085406.6716-6-stephan@gerhold.netSigned-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

Add a few more labels to device nodes declared in msm8916.dtsi
so that we can set all needed properties using labels in the
board-specific device tree part.

Also rename the "otg" label to "usb" to allow grouping it with
the USB PHY (usb_hs_phy) node when ordering referenced labels
alphabetically.
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20200720085406.6716-5-stephan@gerhold.netSigned-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

The leds node does not use any memory regions of the SoC and should
therefore be declared outside the "soc" node.
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20200720085406.6716-4-stephan@gerhold.netSigned-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

The "sound" node in apq8016-sbc.dtsi references memory regions
provided by the SoC and should be therefore declared in msm8916.dtsi.

Additionally, the machine driver used for the "qcom,apq8016-sbc-sndcard"
compatible also works on other MSM8916 devices (provided that audio
routing is set up properly). It is not really specific to apq8016-sbc.

Simplify setting up sound on other boards by moving the common part
to msm8916.dtsi. This also allows referencing the node by the label,
so that we can eventually drop the "soc" node entirely from the
board-specific device tree part and use labels exclusively.

Cc: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20200720085406.6716-3-stephan@gerhold.netSigned-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

apq8016-sbc.dtsi overrides several properties that are already the
default in msm8916.dtsi. Remove these to simplify the device tree
a bit.
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20200720085406.6716-2-stephan@gerhold.netSigned-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

Currently sm8250.dtsi only defines default debug uart. Port rest uart
nodes from the downstream dtsi file.
Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20200909103238.149761-1-dmitry.baryshkov@linaro.orgSigned-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

Add the necessary pinctrl, interrupt property and a suitable sleep config
to support Bluetooth wakeup feature.

GPIO mode is configured in sleep state to drive the RTS/RFR line low.
If QUP function is selected in sleep state, UART RTS/RFR is pulled high
during suspend and BT SoC not able to send wakeup bytes.
Tested-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: satya priya <skakit@codeaurora.org>
Link: https://lore.kernel.org/r/1600091917-7464-4-git-send-email-skakit@codeaurora.orgSigned-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

Add the necessary pinctrl, interrupt property and a suitable sleep config
to support Bluetooth wakeup feature.

GPIO mode is configured in sleep state to drive the RTS/RFR line low.
If QUP function is selected in sleep state, UART RTS/RFR is pulled high
during suspend and BT SoC not able to send wakeup bytes.
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: satya priya <skakit@codeaurora.org>
Link: https://lore.kernel.org/r/1600091917-7464-3-git-send-email-skakit@codeaurora.orgSigned-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

Remove output-high from CTS and TX as this is not really required. During
bringup to fix transfer failures this was added to match with console uart
settings. Probably some boot loader config was missing then. As it is
working fine now, remove it.
Signed-off-by: satya priya <skakit@codeaurora.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Link: https://lore.kernel.org/r/1600091917-7464-2-git-send-email-skakit@codeaurora.orgSigned-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

Some trogdor board variants only have one USB port, so add a couple
labels to these ports so we can modify them later.
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Cc: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Stephen Boyd <swboyd@chromium.org>
Link: https://lore.kernel.org/r/20200914232218.658664-1-swboyd@chromium.orgSigned-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

Also add a space after '=' while at it.
Tested-by: Konrad Dybcio <konradybcio@gmail.com>
Signed-off-by: Łukasz Patron <priv.luk@gmail.com>
Link: https://lore.kernel.org/r/20200725082417.8507-1-priv.luk@gmail.comSigned-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

The number of interrupt cells for the mdss interrupt controller is 1,
meaning there should only be one cell for the interrupt number, not two
where the second cell is the irq flags. Drop the second cell to match
the binding.

Cc: Kalyan Thota <kalyan_t@codeaurora.org>
Cc: Harigovindan P <harigovi@codeaurora.org
Fixes: a3db7ad1 ("arm64: dts: sc7180: add display dt nodes")
Signed-off-by: Stephen Boyd <swboyd@chromium.org>
Link: https://lore.kernel.org/r/20200811192503.1811462-1-swboyd@chromium.orgSigned-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

Document the new device-tree bindings for boards
HK10-C1 and HK10-C2 based on ipq8074 SoC.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
Link: https://lore.kernel.org/r/1596706332-12957-2-git-send-email-gokulsri@codeaurora.orgSigned-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

IPQ8074 has A53 cores, so lets use the corresponding PMU compatible.
Signed-off-by: Kathiravan T <kathirav@codeaurora.org>
Link: https://lore.kernel.org/r/1597642116-15902-1-git-send-email-kathirav@codeaurora.orgSigned-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

Add A53 PLL, APCS clock, RPM Glink, RPM message RAM, cpu-opp-table,
SMPA2 regulator to enable the cpu frequency on IPQ6018.
Co-developed-by: Sivaprakash Murugesan <sivaprak@codeaurora.org>
Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org>
Signed-off-by: Kathiravan T <kathirav@codeaurora.org>
Link: https://lore.kernel.org/r/1597648720-13649-3-git-send-email-kathirav@codeaurora.orgSigned-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

Add the mailbox compatible for the IPQ6018 SoC.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Kathiravan T <kathirav@codeaurora.org>
Link: https://lore.kernel.org/r/1597648720-13649-2-git-send-email-kathirav@codeaurora.orgSigned-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

While the DT parser recognizes "ok" as a valid value for the
"status" property, it is actually mentioned nowhere. Use the
proper value "okay" instead, as done in the majority of files
already.
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
Link: https://lore.kernel.org/r/20200830200845.1771-1-freifunk@adrianschmutzler.deSigned-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>