- 26 Feb, 2024 2 commits
-
-
Josua Mayer authored
Add description for the SolidRun AM642 SoM, and HummingBoard-T evaluation board. The SoM features: - 1x cpsw ethernet with phy - 2x pru ethernet with phy - eMMC - spi flash (assembly option) Additionally microSD and usb-2.0 otg are included in the SoM description as they are supported boot sources for the SOC boot-rom. The Carrier provides: - 3x RJ45 connector - 2x M.2 connector - USB-2.0 Hub - USB-A Connector - LEDs - 2x CAN transceiver - 1x RS485 transceiver - sensors The M.2 connectors support either USB-3.1 or PCI-E depending on status of a mux. By default the mux is switched off. Signed-off-by:
Josua Mayer <josua@solid-run.com> Link: https://lore.kernel.org/r/20240219-add-am64-som-v7-3-0e6e95b0a05d@solid-run.comSigned-off-by:
Vignesh Raghavendra <vigneshr@ti.com>
-
Josua Mayer authored
Add bindings for SolidRun AM642 HummingBoard-T Board, which is the evaluation board for SolidRun AM642 SoM. Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240219-add-am64-som-v7-1-0e6e95b0a05d@solid-run.comSigned-off-by:
-
- 21 Feb, 2024 13 commits
-
-
Brandon Brnich authored
This patch adds support for the Wave521cl on the AM62P. Signed-off-by:
Brandon Brnich <b-brnich@ti.com> Link: https://lore.kernel.org/r/20240220191413.3355007-4-b-brnich@ti.comSigned-off-by:
-
Darren Etheridge authored
Add the Chips and Media wave521cl video decoder/encoder node on J721S2. Signed-off-by:
Darren Etheridge <detheridge@ti.com> Signed-off-by:
-
Brandon Brnich authored
This patch adds support for the Wave521cl on the J784S4-evm. Signed-off-by:
-
Dasnavis Sabiya authored
AM69 SK has S28HS512T OSPI flash connected to MCU OSPI0. Enable support for the same. Also describe the partition information according to the offsets in the bootloader. Reviewed-by:
Udit Kumar <u-kumar1@ti.com> Signed-off-by:
Dasnavis Sabiya <sabiya.d@ti.com> Link: https://lore.kernel.org/r/20240220162527.663394-3-sabiya.d@ti.comSigned-off-by:
-
Dasnavis Sabiya authored
AM69 SK board has several CAN bus interfaces on both MCU and MAIN domains. This enables the CAN interfaces on MCU and MAIN domain. Reviewed-by:
-
Jai Luthra authored
Enable symbols so that overlays can be applied on the base DTB for SK-AM62P. Also compile-test known-to-work camera sensor overlays for OV5640 and IMX219. Reviewed-by:
Vaishnav Achath <vaishnav.a@ti.com> Signed-off-by:
Jai Luthra <j-luthra@ti.com> Link: https://lore.kernel.org/r/20240220-am62p_csi-v2-4-3e71d9945571@ti.comSigned-off-by:
-
Jai Luthra authored
AM62P supports image capture via the MIPI CSI-2 protocol, it uses three IPs to achieve this: Cadence DPHY, Cadence CSI-RX, and TI's pixelgrabber wrapper on top. Add nodes for these IPs in the devicetree, and keep them disabled here, so these may be enabled by the sensor overlays. Reviewed-by:
-
Jai Luthra authored
On AM62P, CSI-RX uses a dedicated BCDMA instance (DMASS1) for transferring captured camera frames to DDR, so enable it. Reviewed-by:
-
Jai Luthra authored
The INTR module for DMASS1 (CSI specific DMASS) is outside the currently available ranges, as it starts at 0x4e400000. So fix the ranges property to enable programming the interrupts correctly. Fixes: 29075cc0 ("arm64: dts: ti: Introduce AM62P5 family of SoCs") Reviewed-by:
-
Vaishnav Achath authored
J722S EVM has S28HS512T 64 MiB Octal SPI NOR flash connected to the OSPI interface, add support for the flash and describe the partition information as per bootloader. Signed-off-by:
-
Siddharth Vadapalli authored
Enable MAC Port 1 of CPSW3G instance of CPSW Ethernet Switch in RGMII-RXID mode of operation. Port 2 is not connected on the EVM, thus keep it disabled. Signed-off-by:
Siddharth Vadapalli <s-vadapalli@ti.com> Signed-off-by:
-
Chintan Vankar authored
Change offset in mux-reg-masks property for serdes_ln_ctrl node since reg-mux property is used in compatible. Fixes: 27651492 ("mux: mmio: use reg property when parent device is not a syscon") Signed-off-by:
Chintan Vankar <c-vankar@ti.com> Acked-by:
Andrew Davis <afd@ti.com> Signed-off-by:
-
Andrew Davis authored
Change offset in mux-reg-masks property for hbmc_mux node since reg-mux property is used in compatible. While here, update the reg region to include 4 bytes as this is a 32bit register. Fixes: 27651492 ("mux: mmio: use reg property when parent device is not a syscon") Suggested-by:
Peter Rosin <peda@axentia.se> Signed-off-by:
-
- 19 Feb, 2024 25 commits
-
-
Devarsh Thakkar authored
This adds common1 register space for AM62A SoC which is using TI's Keystone display hardware and supporting it as described in Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml Fixes: 36188116 ("arm64: dts: ti: k3-am62a-main: Add node for Display SubSystem (DSS)") Signed-off-by:
Devarsh Thakkar <devarsht@ti.com> Reviewed-by:
Tomi Valkeinen <tomi.valkeinen@ideasonboard.com> Reviewed-by:
Aradhya Bhatia <a-bhatia1@ti.com> Link: https://lore.kernel.org/r/20240216062426.4170528-5-devarsht@ti.comSigned-off-by:
-
Devarsh Thakkar authored
This adds common1 register space for AM62x SoC which is using TI's Keystone display hardware and supporting it as described in Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml Fixes: 8ccc1073 ("arm64: dts: ti: k3-am62-main: Add node for DSS") Signed-off-by:
-
Devarsh Thakkar authored
This adds common1 register space for AM65x SoC which is using TI's Keystone display hardware and supporting it as described in Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml Fixes: fc539b90 ("arm64: dts: ti: am654: Add DSS node") Signed-off-by:
-
MD Danish Anwar authored
The am642-evm doesn't allow to enable 2 x CPSW3g ports and 2 x ICSSG1 ports all together, so base k3-am642-evm.dts enables by default 2 x CPSW3g ports and 1 x ICSSG1 ports, but it is also possible to support 1 x CPSW3g ports and 2 x ICSSG1 ports configuration. This patch adds overlay to support 1 x CPSW3g ports and 2 x ICSSG1 ports configuration: - Add label name 'mdio_mux_1' for 'mdio-mux-1' node so that the node 'mdio-mux-1' can be disabled in the overlay using the label name. - disable 2nd CPSW3g port - update CPSW3g pinmuxes to not use RGMII2 - disable mdio-mux-1 and define mdio-mux-2 to route ICSSG1 MDIO to the shared DP83869 PHY - add and enable ICSSG1 RGMII2 pinmuxes - enable ICSSG1 MII1 port Reviewed-by:
Ravi Gunasekaran <r-gunasekaran@ti.com> Reviewed-by:
Roger Quadros <rogerq@kernel.org> Signed-off-by:
MD Danish Anwar <danishanwar@ti.com> Link: https://lore.kernel.org/r/20240215103036.2825096-4-danishanwar@ti.comSigned-off-by:
-
MD Danish Anwar authored
ICSSG1 provides dual Gigabit Ethernet support with proper FW loaded. The ICSSG1 MII0 (RGMII1) has DP83869 PHY attached to it. The ICSSG1 shares MII1 (RGMII2) PHY DP83869 with CPSW3g and it's assigned by default to CPSW3g. The MDIO access to MII1 (RGMII2) PHY DP83869 is controlled by MDIO bus switch and also assigned to CPSW3g. Therefore the ICSSG1 MII1 (RGMII2) port is kept disable and ICSSG1 is enabled in single MAC mode by default. Reviewed-by:
-
Suman Anna authored
The ICSSG IP on AM64x SoCs have two Industrial Ethernet Peripherals (IEPs) to manage/generate Industrial Ethernet functions such as time stamping. Each IEP sub-module is sourced from an internal clock mux that can be derived from either of the IP instance's ICSSG_IEP_GCLK or from another internal ICSSG CORE_CLK mux. Add both the IEP nodes for both the ICSSG instances. The IEP clock is currently configured to be derived indirectly from the ICSSG_ICLK running at 250 MHz. Signed-off-by:
Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by:
Suman Anna <s-anna@ti.com> Reviewed-by:
-
Judith Mendez authored
Add missing bootph-all property for AM62p MMC0 and AM64x MMC0 nodes. Signed-off-by:
Judith Mendez <jm@ti.com> Tested-by:
Wadim Egorov <w.egorov@phytec.de> Link: https://lore.kernel.org/r/20240213235701.2438513-10-jm@ti.comSigned-off-by:
-
Judith Mendez authored
Move bus-width property to *main.dtsi, above the OTAP/ITAP delay values. While there is no error with where it is currently at, it is easier to read the MMC node if the bus-width property is located above the OTAP/ITAP delay values consistently across MMC nodes. Add missing bus-width for MMC2 in k3-am62-main. Signed-off-by:
-
Judith Mendez authored
Move ti,clkbuf-sel property above the OTAP/ITAP delay values. While there is no error with where it is currently at, it is easier to read the MMC node if ti,clkbuf-sel is located above the OTAP/ITAP delay values consistently across MMC nodes. Add missing ti,clkbuf-sel for MMC0 in k3-am64-main. Signed-off-by:
-
Judith Mendez authored
Remove DLL properties which are not applicable for soft PHYs since these PHYs do not have a DLL to enable. Acked-by: Francesco Dolcini <francesco.dolcini@toradex.com> # Verdin AM62 Signed-off-by:
-
Judith Mendez authored
Add OTAP/ITAP values to enable HS400 timing for MMC0 and SDR104 timing for MMC1/MMC2. Remove no-1-8-v property to enable the highest speed mode possible. Update MMC OTAP/ITAP values according to the datasheet [0], refer to Table 7-79 for MMC0 and Table 7-97 for MMC1/MMC2. [0] https://www.ti.com/lit/ds/symlink/am62p.pdfSigned-off-by:
-
Judith Mendez authored
Update MMC0/MMC1 OTAP/ITAP values according to the datasheet [0], refer to Table 7-68 for MMC0 and Table 7-77 for MMC1. [0] https://www.ti.com/lit/ds/symlink/am6442.pdf Fixes: 8abae938 ("arm64: dts: ti: Add support for AM642 SoC") Signed-off-by:
-
Nitin Yadav authored
Add support for 32GB eMMC card on AM62A7 SK. Includes adding mmc0 pins settings. Add mmc0 alias for sdhci0 in k3-am62a7-sk.dts. Signed-off-by:
Nitin Yadav <n-yadav@ti.com> Signed-off-by:
-
Judith Mendez authored
Add sdhci2 DT node in k3-am62a-main for mmc2. Add otap/itap values according to the datasheet[0], Refer to Table 7-97. [0] https://www.ti.com/lit/ds/symlink/am62a3.pdfSigned-off-by:
-
Nitin Yadav authored
Add sdhci0 DT node in k3-am62a-main for eMMC support. Add otap/itap values according to the datasheet[0], refer to Table 7-79. [0] https://www.ti.com/lit/ds/symlink/am62a3.pdfSigned-off-by:
-
Bhavya Kapoor authored
Only Tx and Rx Signal lines for wkup_uart0 are brought out on the J784S4 EVM from SoC, but CTS and RTS signal lines are not brought on the EVM. Thus, remove pinmux for CTS and RTS signal lines for wkup_uart0 in J784S4. Fixes: 6fa5d37a ("arm64: dts: ti: k3-j784s4-evm: Add mcu and wakeup uarts") Signed-off-by:
Bhavya Kapoor <b-kapoor@ti.com> Link: https://lore.kernel.org/r/20240214105846.1096733-5-b-kapoor@ti.comSigned-off-by:
-
Bhavya Kapoor authored
Only Tx and Rx Signal lines for wkup_uart0 are brought out on the Common Proc Board through SoM, but CTS and RTS signal lines are not brought on the board. Thus, remove pinmux for CTS and RTS signal lines for wkup_uart0 in J721S2. Fixes: f5e9ee0b ("arm64: dts: ti: k3-j721s2-common-proc-board: Add uart pinmux") Signed-off-by:
-
Bhavya Kapoor authored
Clock-frequency property is already present in mcu_uart0 node of the k3-j7200-mcu-wakeup.dtsi file. Thus, remove redundant clock-frequency property from mcu_uart0 node. Fixes: 3709ea7f ("arm64: dts: ti: k3-j7200-common-proc-board: Add uart pinmux") Signed-off-by:
-
Bhavya Kapoor authored
WKUP_PADCONFIG registers for wkup_uart0 and mcu_uart0 lies under wkup_pmx2 for J7200. Thus, modify pinmux for both of them. Fixes: 3709ea7f ("arm64: dts: ti: k3-j7200-common-proc-board: Add uart pinmux") Signed-off-by:
-
Vaishnav Achath authored
RPi v2 Camera (IMX219) is an 8MP camera that can be used with SK-AM69, J721E SK, and AM68 SK through the 22-pin CSI-RX connector. Add a reference overlay for dual IMX219 RPI camera v2 modules which can be used across AM68 SK, AM69 SK, TDA4VM SK boards that have a 15/22-pin FFC connector. Also enable build testing and symbols for all the three platforms. Signed-off-by:
-
Vaishnav Achath authored
J784S4 has three CSI2RX capture subsystem featuring Cadence CSI2RX, DPHY and TI's pixel grabbing wrapper. Add nodes for the same and keep them disabled by default. J784S4 uses a dedicated BCDMA instance for CSI-RX traffic, so enable that as well. J784S4 TRM (Section 12.7 Camera Subsystem): https://www.ti.com/lit/zip/spruj52Signed-off-by:
-
Vaishnav Achath authored
J721S2 has two CSI2RX capture subsystem featuring Cadence CSI2RX, DPHY and TI's pixel grabbing wrapper. Add nodes for the same and keep them disabled by default. J721S2 uses a dedicated BCDMA instance for CSI-RX traffic, so enable that as well. J721S2 TRM (Section 12.7 Camera Subsystem): https://www.ti.com/lit/zip/spruj28Signed-off-by:
-
Vaishnav Achath authored
J721E has two CSI2RX capture subsystem featuring Cadence CSI2RX, DPHY and TI's pixel grabbing wrapper. Add nodes for the same and keep them disabled by default. J721E TRM (Section 12.7 Camera Subsystem): https://www.ti.com/lit/zip/spruil1Signed-off-by:
-
Vaishnav Achath authored
J721E SK has the CSI2RX routed to a MIPI CSI connector and to 15-pin RPi camera connector through an analog mux with GPIO control, model that so that an overlay can control the mux state according to connected cameras. Also provide labels to the I2C mux bus instances so that a generic overlay can be used across multiple platforms. J721E SK schematics: https://www.ti.com/lit/zip/sprr438Signed-off-by:
-
Vaishnav Achath authored
CSI cameras are controlled using I2C. On AM69 Starter Kit, this is routed to I2C-1, so enable the instance, TCA9543 I2C switch and the TCA6408 GPIO expander on the bus. AM69 SK has the CSI2RX routed to a MIPI CSI connector and to 22-pin RPi camera connector through an analog mux with GPIO control, model that so that an overlay can control the mux state according to connected cameras. AM69 SK schematics: https://www.ti.com/lit/zip/sprr466Signed-off-by:
-
